Lines Matching +full:can +full:- +full:r8a7791
1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "renesas-cpg-mssr.h"
35 #include "clk-div6.h"
48 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
49 * R-Car Gen2, R-Car Gen3, and RZ/G1.
50 * These are NOT valid for R-Car Gen1 and RZ/A1!
175 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
227 * struct mstp_clock - MSTP gating clock
228 * @hw: handle between common and hardware-specific interfaces
243 struct cpg_mssr_priv *priv = clock->priv; in cpg_rzt2h_mstp_read()
245 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_read()
253 struct cpg_mssr_priv *priv = clock->priv; in cpg_rzt2h_mstp_write()
255 RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0; in cpg_rzt2h_mstp_write()
263 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
264 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
265 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
266 struct device *dev = priv->dev; in cpg_mstp_clock_endisable()
272 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
274 spin_lock_irqsave(&priv->pub.rmw_lock, flags); in cpg_mstp_clock_endisable()
276 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
277 value = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
282 writeb(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
285 readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
286 barrier_data(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
288 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mstp_clock_endisable()
290 priv->control_regs[reg]); in cpg_mstp_clock_endisable()
298 priv->control_regs[reg], in cpg_mstp_clock_endisable()
301 value = readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
306 writel(value, priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
309 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); in cpg_mstp_clock_endisable()
311 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
314 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mstp_clock_endisable()
316 * For the RZ/T2H case, it is necessary to perform a read-back after in cpg_mstp_clock_endisable()
317 * accessing the MSTPCRm register and to dummy-read any register of in cpg_mstp_clock_endisable()
318 * the IP at least seven times. Instead of memory-mapping the IP in cpg_mstp_clock_endisable()
321 cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]); in cpg_mstp_clock_endisable()
326 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], in cpg_mstp_clock_endisable()
330 priv->pub.base0 + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
348 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
349 unsigned int reg = clock->index / 32; in cpg_mstp_clock_is_enabled()
352 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
353 value = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mstp_clock_is_enabled()
354 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) in cpg_mstp_clock_is_enabled()
356 priv->control_regs[reg]); in cpg_mstp_clock_is_enabled()
358 value = readl(priv->pub.base0 + priv->status_regs[reg]); in cpg_mstp_clock_is_enabled()
360 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
373 unsigned int clkidx = clkspec->args[1]; in cpg_mssr_clk_src_twocell_get()
375 struct device *dev = priv->dev; in cpg_mssr_clk_src_twocell_get()
381 switch (clkspec->args[0]) { in cpg_mssr_clk_src_twocell_get()
384 if (clkidx > priv->last_dt_core_clk) { in cpg_mssr_clk_src_twocell_get()
387 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
389 clk = priv->clks[clkidx]; in cpg_mssr_clk_src_twocell_get()
394 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
396 range_check = 7 - (clkidx % 10); in cpg_mssr_clk_src_twocell_get()
399 range_check = 31 - (clkidx % 100); in cpg_mssr_clk_src_twocell_get()
401 if (range_check < 0 || idx >= priv->num_mod_clks) { in cpg_mssr_clk_src_twocell_get()
404 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
406 clk = priv->clks[priv->num_core_clks + idx]; in cpg_mssr_clk_src_twocell_get()
410 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
411 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
419 clkspec->args[0], clkspec->args[1], clk, in cpg_mssr_clk_src_twocell_get()
428 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; in cpg_mssr_register_core_clk()
429 struct device *dev = priv->dev; in cpg_mssr_register_core_clk()
430 unsigned int id = core->id, div = core->div; in cpg_mssr_register_core_clk()
433 WARN_DEBUG(id >= priv->num_core_clks); in cpg_mssr_register_core_clk()
434 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_core_clk()
436 switch (core->type) { in cpg_mssr_register_core_clk()
438 clk = of_clk_get_by_name(priv->np, core->name); in cpg_mssr_register_core_clk()
444 WARN_DEBUG(core->parent >= priv->num_core_clks); in cpg_mssr_register_core_clk()
445 parent = priv->pub.clks[core->parent]; in cpg_mssr_register_core_clk()
453 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()
455 div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1; in cpg_mssr_register_core_clk()
457 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()
458 clk = cpg_div6_register(core->name, 1, &parent_name, in cpg_mssr_register_core_clk()
459 priv->pub.base0 + core->offset, in cpg_mssr_register_core_clk()
460 &priv->pub.notifiers); in cpg_mssr_register_core_clk()
462 clk = clk_register_fixed_factor(NULL, core->name, in cpg_mssr_register_core_clk()
464 core->mult, div); in cpg_mssr_register_core_clk()
469 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, in cpg_mssr_register_core_clk()
470 core->mult); in cpg_mssr_register_core_clk()
474 if (info->cpg_clk_register) in cpg_mssr_register_core_clk()
475 clk = info->cpg_clk_register(dev, core, info, in cpg_mssr_register_core_clk()
476 &priv->pub); in cpg_mssr_register_core_clk()
479 core->name, core->type); in cpg_mssr_register_core_clk()
487 priv->pub.clks[id] = clk; in cpg_mssr_register_core_clk()
492 core->name, PTR_ERR(clk)); in cpg_mssr_register_core_clk()
500 struct device *dev = priv->dev; in cpg_mssr_register_mod_clk()
501 unsigned int id = mod->id; in cpg_mssr_register_mod_clk()
507 WARN_DEBUG(id < priv->num_core_clks); in cpg_mssr_register_mod_clk()
508 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
509 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
510 WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT); in cpg_mssr_register_mod_clk()
512 if (!mod->name) { in cpg_mssr_register_mod_clk()
517 parent = priv->pub.clks[mod->parent]; in cpg_mssr_register_mod_clk()
525 clk = ERR_PTR(-ENOMEM); in cpg_mssr_register_mod_clk()
529 init.name = mod->name; in cpg_mssr_register_mod_clk()
536 clock->index = id - priv->num_core_clks; in cpg_mssr_register_mod_clk()
537 clock->priv = priv; in cpg_mssr_register_mod_clk()
538 clock->hw.init = &init; in cpg_mssr_register_mod_clk()
540 for (i = 0; i < info->num_crit_mod_clks; i++) in cpg_mssr_register_mod_clk()
541 if (id == info->crit_mod_clks[i] && in cpg_mssr_register_mod_clk()
542 cpg_mstp_clock_is_enabled(&clock->hw)) { in cpg_mssr_register_mod_clk()
544 mod->name); in cpg_mssr_register_mod_clk()
554 for (i = 0; i < priv->num_reserved_ids; i++) { in cpg_mssr_register_mod_clk()
555 if (id == priv->reserved_ids[i]) { in cpg_mssr_register_mod_clk()
556 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); in cpg_mssr_register_mod_clk()
562 clk = clk_register(NULL, &clock->hw); in cpg_mssr_register_mod_clk()
567 priv->clks[id] = clk; in cpg_mssr_register_mod_clk()
568 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); in cpg_mssr_register_mod_clk()
573 mod->name, PTR_ERR(clk)); in cpg_mssr_register_mod_clk()
590 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in cpg_mssr_is_pm_clk()
593 switch (clkspec->args[0]) { in cpg_mssr_is_pm_clk()
595 for (i = 0; i < pd->num_core_pm_clks; i++) in cpg_mssr_is_pm_clk()
596 if (clkspec->args[1] == pd->core_pm_clks[i]) in cpg_mssr_is_pm_clk()
611 struct device_node *np = dev->of_node; in cpg_mssr_attach_dev()
619 return -EPROBE_DEFER; in cpg_mssr_attach_dev()
622 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in cpg_mssr_attach_dev()
672 struct device_node *np = dev->of_node; in cpg_mssr_add_clk_domain()
680 return -ENOMEM; in cpg_mssr_add_clk_domain()
682 pd->num_core_pm_clks = num_core_pm_clks; in cpg_mssr_add_clk_domain()
683 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); in cpg_mssr_add_clk_domain()
685 genpd = &pd->genpd; in cpg_mssr_add_clk_domain()
686 genpd->name = np->name; in cpg_mssr_add_clk_domain()
687 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in cpg_mssr_add_clk_domain()
689 genpd->attach_dev = cpg_mssr_attach_dev; in cpg_mssr_add_clk_domain()
690 genpd->detach_dev = cpg_mssr_detach_dev; in cpg_mssr_add_clk_domain()
714 const u16 off = set ? priv->reset_regs[reg] : priv->reset_clear_regs[reg]; in cpg_mssr_reset_operate()
718 dev_dbg(priv->dev, "%s %u%02u\n", func, reg, bit); in cpg_mssr_reset_operate()
720 writel(bitmask, priv->pub.base0 + off); in cpg_mssr_reset_operate()
721 readl(priv->pub.base0 + off); in cpg_mssr_reset_operate()
722 barrier_data(priv->pub.base0 + off); in cpg_mssr_reset_operate()
736 * On R-Car Gen4, delay after SRCR has been written is 1ms. in cpg_mssr_reset()
740 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) in cpg_mssr_reset()
768 return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask); in cpg_mssr_status()
783 dev_dbg(priv->dev, "%s %u%02u\n", set ? "assert" : "deassert", reg, bit); in cpg_mrcr_set_reset_state()
785 spin_lock_irqsave(&priv->pub.rmw_lock, flags); in cpg_mrcr_set_reset_state()
787 reg_addr = priv->pub.base0 + priv->reset_regs[reg]; in cpg_mrcr_set_reset_state()
806 dev_err(priv->dev, "Reset register %u%02u operation failed\n", reg, bit); in cpg_mrcr_set_reset_state()
807 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); in cpg_mrcr_set_reset_state()
808 return -EIO; in cpg_mrcr_set_reset_state()
811 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); in cpg_mrcr_set_reset_state()
855 unsigned int unpacked = reset_spec->args[0]; in cpg_mssr_reset_xlate()
858 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { in cpg_mssr_reset_xlate()
859 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); in cpg_mssr_reset_xlate()
860 return -EINVAL; in cpg_mssr_reset_xlate()
873 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_reset_controller_register()
874 priv->rcdev.ops = &cpg_mrcr_reset_ops; in cpg_mssr_reset_controller_register()
875 priv->rcdev.nr_resets = ARRAY_SIZE(mrcr_for_rzt2h) * 32; in cpg_mssr_reset_controller_register()
877 priv->rcdev.ops = &cpg_mssr_reset_ops; in cpg_mssr_reset_controller_register()
878 priv->rcdev.nr_resets = priv->num_mod_clks; in cpg_mssr_reset_controller_register()
881 priv->rcdev.of_node = priv->dev->of_node; in cpg_mssr_reset_controller_register()
882 priv->rcdev.of_reset_n_cells = 1; in cpg_mssr_reset_controller_register()
883 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; in cpg_mssr_reset_controller_register()
885 return devm_reset_controller_register(priv->dev, &priv->rcdev); in cpg_mssr_reset_controller_register()
898 .compatible = "renesas,r7s9210-cpg-mssr",
904 .compatible = "renesas,r8a7742-cpg-mssr",
910 .compatible = "renesas,r8a7743-cpg-mssr",
915 .compatible = "renesas,r8a7744-cpg-mssr",
921 .compatible = "renesas,r8a7745-cpg-mssr",
927 .compatible = "renesas,r8a77470-cpg-mssr",
933 .compatible = "renesas,r8a774a1-cpg-mssr",
939 .compatible = "renesas,r8a774b1-cpg-mssr",
945 .compatible = "renesas,r8a774c0-cpg-mssr",
951 .compatible = "renesas,r8a774e1-cpg-mssr",
957 .compatible = "renesas,r8a7790-cpg-mssr",
963 .compatible = "renesas,r8a7791-cpg-mssr",
966 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
968 .compatible = "renesas,r8a7793-cpg-mssr",
974 .compatible = "renesas,r8a7792-cpg-mssr",
980 .compatible = "renesas,r8a7794-cpg-mssr",
986 .compatible = "renesas,r8a7795-cpg-mssr",
992 .compatible = "renesas,r8a7796-cpg-mssr",
998 .compatible = "renesas,r8a77961-cpg-mssr",
1004 .compatible = "renesas,r8a77965-cpg-mssr",
1010 .compatible = "renesas,r8a77970-cpg-mssr",
1016 .compatible = "renesas,r8a77980-cpg-mssr",
1022 .compatible = "renesas,r8a77990-cpg-mssr",
1028 .compatible = "renesas,r8a77995-cpg-mssr",
1034 .compatible = "renesas,r8a779a0-cpg-mssr",
1040 .compatible = "renesas,r8a779f0-cpg-mssr",
1046 .compatible = "renesas,r8a779g0-cpg-mssr",
1052 .compatible = "renesas,r8a779h0-cpg-mssr",
1058 .compatible = "renesas,r9a09g077-cpg-mssr",
1064 .compatible = "renesas,r9a09g087-cpg-mssr",
1082 /* This is the best we can do to check for the presence of PSCI */ in cpg_mssr_suspend_noirq()
1087 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_suspend_noirq()
1088 if (priv->smstpcr_saved[reg].mask) in cpg_mssr_suspend_noirq()
1089 priv->smstpcr_saved[reg].val = in cpg_mssr_suspend_noirq()
1090 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
1091 readb(priv->pub.base0 + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()
1092 readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_suspend_noirq()
1096 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL); in cpg_mssr_suspend_noirq()
1108 /* This is the best we can do to check for the presence of PSCI */ in cpg_mssr_resume_noirq()
1113 raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL); in cpg_mssr_resume_noirq()
1116 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_resume_noirq()
1117 mask = priv->smstpcr_saved[reg].mask; in cpg_mssr_resume_noirq()
1121 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
1122 oldval = readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1124 oldval = readl(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1126 newval |= priv->smstpcr_saved[reg].val & mask; in cpg_mssr_resume_noirq()
1130 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
1131 writeb(newval, priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1133 readb(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1134 barrier_data(priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1137 writel(newval, priv->pub.base0 + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
1140 mask &= ~priv->smstpcr_saved[reg].val; in cpg_mssr_resume_noirq()
1144 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], in cpg_mssr_resume_noirq()
1165 kfree(priv->reserved_ids); in cpg_mssr_reserved_exit()
1179 * to a non-Linux system will be disabled when Linux is booted. in cpg_mssr_reserved_init()
1181 * To avoid such situation, renesas-cpg-mssr assumes the device which has in cpg_mssr_reserved_init()
1182 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag in cpg_mssr_reserved_init()
1200 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { in cpg_mssr_reserved_init()
1204 if (it.node != priv->np) in cpg_mssr_reserved_init()
1217 return -ENOMEM; in cpg_mssr_reserved_init()
1221 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1226 ids[num] = info->num_total_core_clks + idx; in cpg_mssr_reserved_init()
1232 priv->num_reserved_ids = num; in cpg_mssr_reserved_init()
1233 priv->reserved_ids = ids; in cpg_mssr_reserved_init()
1246 if (info->init) { in cpg_mssr_common_init()
1247 error = info->init(dev); in cpg_mssr_common_init()
1252 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in cpg_mssr_common_init()
1255 return -ENOMEM; in cpg_mssr_common_init()
1257 priv->pub.clks = priv->clks; in cpg_mssr_common_init()
1258 priv->np = np; in cpg_mssr_common_init()
1259 priv->dev = dev; in cpg_mssr_common_init()
1260 spin_lock_init(&priv->pub.rmw_lock); in cpg_mssr_common_init()
1262 priv->pub.base0 = of_iomap(np, 0); in cpg_mssr_common_init()
1263 if (!priv->pub.base0) { in cpg_mssr_common_init()
1264 error = -ENOMEM; in cpg_mssr_common_init()
1267 if (info->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_common_init()
1268 priv->pub.base1 = of_iomap(np, 1); in cpg_mssr_common_init()
1269 if (!priv->pub.base1) { in cpg_mssr_common_init()
1270 error = -ENOMEM; in cpg_mssr_common_init()
1275 priv->num_core_clks = info->num_total_core_clks; in cpg_mssr_common_init()
1276 priv->num_mod_clks = info->num_hw_mod_clks; in cpg_mssr_common_init()
1277 priv->last_dt_core_clk = info->last_dt_core_clk; in cpg_mssr_common_init()
1278 RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers); in cpg_mssr_common_init()
1279 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
1280 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { in cpg_mssr_common_init()
1281 priv->status_regs = mstpsr; in cpg_mssr_common_init()
1282 priv->control_regs = smstpcr; in cpg_mssr_common_init()
1283 priv->reset_regs = srcr; in cpg_mssr_common_init()
1284 priv->reset_clear_regs = srstclr; in cpg_mssr_common_init()
1285 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_common_init()
1286 priv->control_regs = stbcr; in cpg_mssr_common_init()
1287 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { in cpg_mssr_common_init()
1288 priv->control_regs = mstpcr_for_rzt2h; in cpg_mssr_common_init()
1289 priv->reset_regs = mrcr_for_rzt2h; in cpg_mssr_common_init()
1290 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { in cpg_mssr_common_init()
1291 priv->status_regs = mstpsr_for_gen4; in cpg_mssr_common_init()
1292 priv->control_regs = mstpcr_for_gen4; in cpg_mssr_common_init()
1293 priv->reset_regs = srcr_for_gen4; in cpg_mssr_common_init()
1294 priv->reset_clear_regs = srstclr_for_gen4; in cpg_mssr_common_init()
1296 error = -EINVAL; in cpg_mssr_common_init()
1301 priv->pub.clks[i] = ERR_PTR(-ENOENT); in cpg_mssr_common_init()
1318 if (priv->pub.base0) in cpg_mssr_common_init()
1319 iounmap(priv->pub.base0); in cpg_mssr_common_init()
1320 if (priv->pub.base1) in cpg_mssr_common_init()
1321 iounmap(priv->pub.base1); in cpg_mssr_common_init()
1337 for (i = 0; i < info->num_early_core_clks; i++) in cpg_mssr_early_init()
1338 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, in cpg_mssr_early_init()
1341 for (i = 0; i < info->num_early_mod_clks; i++) in cpg_mssr_early_init()
1342 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, in cpg_mssr_early_init()
1349 struct device *dev = &pdev->dev; in cpg_mssr_probe()
1350 struct device_node *np = dev->of_node; in cpg_mssr_probe()
1359 error = cpg_mssr_common_init(dev, dev->of_node, info); in cpg_mssr_probe()
1365 priv->dev = dev; in cpg_mssr_probe()
1368 for (i = 0; i < info->num_core_clks; i++) in cpg_mssr_probe()
1369 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); in cpg_mssr_probe()
1371 for (i = 0; i < info->num_mod_clks; i++) in cpg_mssr_probe()
1372 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); in cpg_mssr_probe()
1380 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, in cpg_mssr_probe()
1381 info->num_core_pm_clks); in cpg_mssr_probe()
1386 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_probe()
1399 .name = "renesas-cpg-mssr",