86 	u32 cr0 = readl(pll_clk->pllcr0_reg);  in cpg_pll_8_25_clk_recalc_rate()  local
90 	ni = (FIELD_GET(CPG_PLLxCR0_NI8, cr0) + 1) * 2;  in cpg_pll_8_25_clk_recalc_rate()
92 	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {  in cpg_pll_8_25_clk_recalc_rate()
105 	u32 cr0 = readl(pll_clk->pllcr0_reg);  in cpg_pll_8_25_clk_determine_rate()  local
114 	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {  in cpg_pll_8_25_clk_determine_rate()
139 	u32 cr0 = readl(pll_clk->pllcr0_reg);  in cpg_pll_8_25_clk_set_rate()  local
143 	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {  in cpg_pll_8_25_clk_set_rate()
163 	if (cr0 & CPG_PLLxCR0_SSMODE_FM)  in cpg_pll_8_25_clk_set_rate()
200 	u32 cr0 = readl(pll_clk->pllcr0_reg);  in cpg_pll_9_24_clk_recalc_rate()  local
204 	ni = FIELD_GET(CPG_PLLxCR0_NI9, cr0) + 1;  in cpg_pll_9_24_clk_recalc_rate()
206 	if (cr0 & CPG_PLLxCR0_SSMODE_FM) {  in cpg_pll_9_24_clk_recalc_rate()
226 	static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = {  in cpg_pll_clk_register()  member
247 	pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 1].cr0;  in cpg_pll_clk_register()