Lines Matching +full:fixed +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
62 return parent_rate * mult * pll_clk->fixed_mult;
72 prate = req->best_parent_rate * pll_clk->fixed_mult;
73 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
74 max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
76 return -EINVAL;
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
81 req->rate = prate * mult;
85 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
95 val = readl(pll_clk->pllcr_reg);
97 val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
98 writel(val, pll_clk->pllcr_reg);
100 for (i = 1000; i; i--) {
101 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
107 return -ETIMEDOUT;
130 return ERR_PTR(-ENOMEM);
137 pll_clk->hw.init = &init;
138 pll_clk->pllcr_reg = base + offset;
139 pll_clk->pllecr_reg = base + CPG_PLLECR;
140 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
141 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
143 clk = clk_register(NULL, &pll_clk->hw);
154 * prepare - clk_prepare only ensures that parents are prepared
155 * enable - clk_enable only ensures that parents are enabled
156 * rate - rate is adjustable.
157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
158 * parent - fixed parent. No clk_set_parent support
168 unsigned long max_rate; /* Maximum rate for normal mode */
182 val = readl(zclk->reg) & zclk->mask;
183 mult = 32 - (val >> __ffs(zclk->mask));
186 32 * zclk->fixed_div);
194 unsigned long rate, prate;
196 rate = min(req->rate, req->max_rate);
197 if (rate <= zclk->max_rate) {
198 /* Set parent rate to initial value for normal modes */
199 prate = zclk->max_rate;
201 /* Set increased parent rate for boost modes */
202 prate = rate;
204 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
205 prate * zclk->fixed_div);
207 prate = req->best_parent_rate / zclk->fixed_div;
208 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
209 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
211 return -EINVAL;
213 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
216 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
220 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
227 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
231 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
232 return -EBUSY;
234 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
240 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
246 * ~10 iterations are needed, independently of the CPU rate.
247 * Since this value might be dependent on external xtal rate, pll1
248 * rate or even the other emulation clocks rate, use 1000 as a
251 for (i = 1000; i; i--) {
252 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
258 return -ETIMEDOUT;
281 return ERR_PTR(-ENOMEM);
289 zclk->reg = reg + fcr;
290 zclk->kick_reg = reg + CPG_FRQCRB;
291 zclk->hw.init = &init;
292 zclk->mask = GENMASK(offset + 4, offset);
293 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
295 clk = clk_register(NULL, &zclk->hw);
301 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
302 zclk->fixed_div;
350 struct raw_notifier_head *notifiers = &pub->notifiers;
351 void __iomem *base = pub->base0;
352 struct clk **clks = pub->clks;
358 parent = clks[core->parent & 0xffff]; /* some types use high bits */
362 switch (core->type) {
364 div = cpg_pll_config->extal_div;
373 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
377 mult = cpg_pll_config->pll1_mult;
378 div = cpg_pll_config->pll1_div;
387 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
391 mult = cpg_pll_config->pll3_mult;
392 div = cpg_pll_config->pll3_div;
398 * fixed factor clock for now as there's no generic multiplier
407 return cpg_sdh_clk_register(core->name, base + core->offset,
411 return cpg_sd_clk_register(core->name, base + core->offset,
420 return ERR_PTR(-ENOMEM);
422 csn->reg = base + CPG_RCKCR;
428 value = readl(csn->reg) & 0x3f;
435 writel(value, csn->reg);
447 * Clock selectable between two parents and two fixed dividers
450 if (cpg_mode & BIT(core->offset)) {
451 div = core->div & 0xffff;
453 parent = clks[core->parent >> 16];
456 div = core->div >> 16;
462 return cpg_z_clk_register(core->name, __clk_get_name(parent),
463 base, core->div, core->offset);
466 return cpg_zg_clk_register(core->name, __clk_get_name(parent),
467 base, core->div, core->offset);
471 * Clock combining OSC EXTAL predivider and a fixed divider
473 div = cpg_pll_config->osc_prediv * core->div;
478 * Clock selectable between two parents and two fixed dividers
482 div = core->div & 0xffff;
484 parent = clks[core->parent >> 16];
487 div = core->div >> 16;
492 return clk_register_divider_table(NULL, core->name,
500 * Register RPCSRC as fixed factor clock based on the
514 parent = clks[core->parent >> 16];
517 div = core->div;
527 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
531 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
535 return ERR_PTR(-EINVAL);
538 return clk_register_fixed_factor(NULL, core->name,
552 cpg_quirks = (uintptr_t)attr->data;