1 // SPDX-License-Identifier: GPL-2.0
3  * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
22 #define CPG_FRQCRB_KICK		BIT(31)
39  * prepare - clk_prepare only ensures that parents are prepared
40  * enable - clk_enable only ensures that parents are enabled
41  * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
42  * parent - fixed parent.  No clk_set_parent support
60 	val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;  in cpg_z_clk_recalc_rate()
61 	mult = 32 - val;  in cpg_z_clk_recalc_rate()
69 	unsigned long prate = req->best_parent_rate;  in cpg_z_clk_determine_rate()
72 	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);  in cpg_z_clk_determine_rate()
73 	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);  in cpg_z_clk_determine_rate()
75 		return -EINVAL;  in cpg_z_clk_determine_rate()
77 	mult = div64_ul(req->rate * 32ULL, prate);  in cpg_z_clk_determine_rate()
80 	req->rate = div_u64((u64)prate * mult, 32);  in cpg_z_clk_determine_rate()
95 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)  in cpg_z_clk_set_rate()
96 		return -EBUSY;  in cpg_z_clk_set_rate()
98 	val = readl(zclk->reg);  in cpg_z_clk_set_rate()
100 	val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;  in cpg_z_clk_set_rate()
101 	writel(val, zclk->reg);  in cpg_z_clk_set_rate()
104 	 * Set KICK bit in FRQCRB to update hardware setting and wait for  in cpg_z_clk_set_rate()
107 	kick = readl(zclk->kick_reg);  in cpg_z_clk_set_rate()
109 	writel(kick, zclk->kick_reg);  in cpg_z_clk_set_rate()
120 	for (i = 1000; i; i--) {  in cpg_z_clk_set_rate()
121 		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))  in cpg_z_clk_set_rate()
127 	return -ETIMEDOUT;  in cpg_z_clk_set_rate()
146 		return ERR_PTR(-ENOMEM);  in cpg_z_clk_register()
153 	zclk->reg = base + CPG_FRQCRC;  in cpg_z_clk_register()
154 	zclk->kick_reg = base + CPG_FRQCRB;  in cpg_z_clk_register()
155 	zclk->hw.init = &init;  in cpg_z_clk_register()
157 	clk = clk_register(NULL, &zclk->hw);  in cpg_z_clk_register()
174 		return ERR_PTR(-ENOMEM);  in cpg_rcan_clk_register()
176 	fixed->mult = 1;  in cpg_rcan_clk_register()
177 	fixed->div = 6;  in cpg_rcan_clk_register()
182 		return ERR_PTR(-ENOMEM);  in cpg_rcan_clk_register()
185 	gate->reg = base + CPG_RCANCKCR;  in cpg_rcan_clk_register()
186 	gate->bit_idx = 8;  in cpg_rcan_clk_register()
187 	gate->flags = CLK_GATE_SET_TO_DISABLE;  in cpg_rcan_clk_register()
188 	gate->lock = &cpg_lock;  in cpg_rcan_clk_register()
191 				     &fixed->hw, &clk_fixed_factor_ops,  in cpg_rcan_clk_register()
192 				     &gate->hw, &clk_gate_ops, 0);  in cpg_rcan_clk_register()
205 	{ 10, 36 }, { 11, 48 }, {  0,  0 },
218 		return ERR_PTR(-ENOMEM);  in cpg_adsp_clk_register()
220 	div->reg = base + CPG_ADSPCKCR;  in cpg_adsp_clk_register()
221 	div->width = 4;  in cpg_adsp_clk_register()
222 	div->table = cpg_adsp_div_table;  in cpg_adsp_clk_register()
223 	div->lock = &cpg_lock;  in cpg_adsp_clk_register()
228 		return ERR_PTR(-ENOMEM);  in cpg_adsp_clk_register()
231 	gate->reg = base + CPG_ADSPCKCR;  in cpg_adsp_clk_register()
232 	gate->bit_idx = 8;  in cpg_adsp_clk_register()
233 	gate->flags = CLK_GATE_SET_TO_DISABLE;  in cpg_adsp_clk_register()
234 	gate->lock = &cpg_lock;  in cpg_adsp_clk_register()
237 				     &div->hw, &clk_divider_ops,  in cpg_adsp_clk_register()
238 				     &gate->hw, &clk_gate_ops, 0);  in cpg_adsp_clk_register()
251 	{  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
256 	{  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
265 #define SD_SKIP_FIRST	BIT(0)		/* Skip first clock in SD table */
287 	parent = clks[core->parent];  in rcar_gen2_cpg_clk_register()
293 	switch (core->type) {  in rcar_gen2_cpg_clk_register()
294 	/* R-Car Gen2 */  in rcar_gen2_cpg_clk_register()
296 		div = cpg_pll_config->extal_div;  in rcar_gen2_cpg_clk_register()
301 		 * PLL0 is a  configurable multiplier clock except on R-Car  in rcar_gen2_cpg_clk_register()
306 		mult = cpg_pll_config->pll0_mult;  in rcar_gen2_cpg_clk_register()
317 		mult = cpg_pll_config->pll1_mult / 2;  in rcar_gen2_cpg_clk_register()
321 		mult = cpg_pll_config->pll3_mult;  in rcar_gen2_cpg_clk_register()
325 		return cpg_z_clk_register(core->name, parent_name, base);  in rcar_gen2_cpg_clk_register()
328 		div = cpg_mode & BIT(18) ? 36 : 24;  in rcar_gen2_cpg_clk_register()
332 		return cpg_adsp_clk_register(core->name, parent_name, base);  in rcar_gen2_cpg_clk_register()
356 		div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ?  in rcar_gen2_cpg_clk_register()
361 		return cpg_rcan_clk_register(core->name, parent_name, base);  in rcar_gen2_cpg_clk_register()
364 		return ERR_PTR(-EINVAL);  in rcar_gen2_cpg_clk_register()
368 		return clk_register_fixed_factor(NULL, core->name, parent_name,  in rcar_gen2_cpg_clk_register()
371 		return clk_register_divider_table(NULL, core->name,  in rcar_gen2_cpg_clk_register()
387 		cpg_quirks = (uintptr_t)attr->data;  in rcar_gen2_cpg_init()