Lines Matching full:5
137 BUS_MSTOP(5, BIT(9))),
146 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
149 BUS_MSTOP(3, BIT(5))),
151 BUS_MSTOP(5, BIT(10))),
153 BUS_MSTOP(5, BIT(11))),
154 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
175 BUS_MSTOP(5, BIT(12))),
176 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
177 BUS_MSTOP(5, BIT(12))),
178 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
179 BUS_MSTOP(5, BIT(13))),
180 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
181 BUS_MSTOP(5, BIT(13))),
188 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
195 BUS_MSTOP(1, BIT(5))),
202 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
204 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
206 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
208 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
210 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
212 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
214 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
216 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
218 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
220 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
222 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
224 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
226 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
228 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
230 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
232 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
234 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
242 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
243 BUS_MSTOP(9, BIT(5))),
245 BUS_MSTOP(9, BIT(5))),
247 BUS_MSTOP(9, BIT(5))),
273 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
274 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
285 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
286 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
290 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
306 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
307 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
308 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
309 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
310 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
311 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
312 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
313 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
314 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
315 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
316 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */