Lines Matching full:13
155 BUS_MSTOP(2, BIT(13))),
159 BUS_MSTOP(11, BIT(13))),
170 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
179 BUS_MSTOP(5, BIT(13))),
181 BUS_MSTOP(5, BIT(13))),
185 BUS_MSTOP(3, BIT(13))),
222 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
236 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
238 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
240 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
242 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
244 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
246 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
248 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
250 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
252 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
254 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
256 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
258 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
278 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
295 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
296 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
304 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
315 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
318 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
319 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
320 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
321 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */