Lines Matching +full:11 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
203 BUS_MSTOP(10, BIT(11))),
213 BUS_MSTOP(5, BIT(11))),
218 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
219 BUS_MSTOP(11, BIT(13))),
221 BUS_MSTOP(11, BIT(14))),
223 BUS_MSTOP(11, BIT(15))),
226 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
243 BUS_MSTOP(11, BIT(0))),
245 BUS_MSTOP(11, BIT(0))),
247 BUS_MSTOP(11, BIT(0))),
248 DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
249 BUS_MSTOP(11, BIT(1))),
251 BUS_MSTOP(11, BIT(1))),
253 BUS_MSTOP(11, BIT(1))),
255 BUS_MSTOP(11, BIT(2))),
256 DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
257 BUS_MSTOP(11, BIT(2))),
259 BUS_MSTOP(11, BIT(2))),
276 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
283 BUS_MSTOP(1, BIT(7))),
284 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
308 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
316 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
317 BUS_MSTOP(7, BIT(7))),
318 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
319 BUS_MSTOP(7, BIT(8))),
320 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
321 BUS_MSTOP(7, BIT(9))),
322 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
323 BUS_MSTOP(7, BIT(10))),
324 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
325 BUS_MSTOP(7, BIT(11))),
326 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
330 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
332 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
334 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
336 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
338 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
340 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
360 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
368 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
369 BUS_MSTOP(9, BIT(7))),
371 BUS_MSTOP(9, BIT(7))),
373 BUS_MSTOP(9, BIT(7))),
374 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
376 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
378 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
389 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
395 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
396 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
397 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
398 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
399 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
400 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
401 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
402 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
403 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
404 DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
405 DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
406 DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
407 DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
408 DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
411 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
412 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
424 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
431 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
432 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
435 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
439 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */