Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
105 {1, 10},
197 BUS_MSTOP(5, BIT(9))),
199 BUS_MSTOP(3, BIT(2))),
201 BUS_MSTOP(3, BIT(3))),
203 BUS_MSTOP(10, BIT(11))),
205 BUS_MSTOP(10, BIT(12))),
209 BUS_MSTOP(3, BIT(5))),
211 BUS_MSTOP(5, BIT(10))),
213 BUS_MSTOP(5, BIT(11))),
215 BUS_MSTOP(2, BIT(13))),
217 BUS_MSTOP(2, BIT(14))),
219 BUS_MSTOP(11, BIT(13))),
221 BUS_MSTOP(11, BIT(14))),
223 BUS_MSTOP(11, BIT(15))),
224 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
225 BUS_MSTOP(12, BIT(0))),
227 BUS_MSTOP(3, BIT(10))),
229 BUS_MSTOP(3, BIT(10))),
231 BUS_MSTOP(1, BIT(0))),
233 BUS_MSTOP(1, BIT(0))),
235 BUS_MSTOP(5, BIT(12))),
237 BUS_MSTOP(5, BIT(12))),
239 BUS_MSTOP(5, BIT(13))),
241 BUS_MSTOP(5, BIT(13))),
243 BUS_MSTOP(11, BIT(0))),
245 BUS_MSTOP(11, BIT(0))),
247 BUS_MSTOP(11, BIT(0))),
249 BUS_MSTOP(11, BIT(1))),
251 BUS_MSTOP(11, BIT(1))),
253 BUS_MSTOP(11, BIT(1))),
254 DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
255 BUS_MSTOP(11, BIT(2))),
257 BUS_MSTOP(11, BIT(2))),
259 BUS_MSTOP(11, BIT(2))),
261 BUS_MSTOP(3, BIT(14))),
263 BUS_MSTOP(10, BIT(15))),
265 BUS_MSTOP(10, BIT(15))),
267 BUS_MSTOP(10, BIT(15))),
269 BUS_MSTOP(3, BIT(13))),
271 BUS_MSTOP(1, BIT(1))),
273 BUS_MSTOP(1, BIT(2))),
275 BUS_MSTOP(1, BIT(3))),
277 BUS_MSTOP(1, BIT(4))),
279 BUS_MSTOP(1, BIT(5))),
281 BUS_MSTOP(1, BIT(6))),
282 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
283 BUS_MSTOP(1, BIT(7))),
285 BUS_MSTOP(1, BIT(8))),
287 BUS_MSTOP(4, BIT(5))),
288 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
289 BUS_MSTOP(4, BIT(5))),
290 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
291 BUS_MSTOP(4, BIT(5))),
292 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
293 BUS_MSTOP(8, BIT(2))),
294 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
295 BUS_MSTOP(8, BIT(2))),
296 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
297 BUS_MSTOP(8, BIT(2))),
298 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
299 BUS_MSTOP(8, BIT(2))),
300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
301 BUS_MSTOP(8, BIT(3))),
302 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
303 BUS_MSTOP(8, BIT(3))),
304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
305 BUS_MSTOP(8, BIT(3))),
306 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
307 BUS_MSTOP(8, BIT(3))),
308 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
309 BUS_MSTOP(8, BIT(4))),
310 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
311 BUS_MSTOP(8, BIT(4))),
312 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
313 BUS_MSTOP(8, BIT(4))),
314 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
315 BUS_MSTOP(8, BIT(4))),
317 BUS_MSTOP(7, BIT(7))),
319 BUS_MSTOP(7, BIT(8))),
321 BUS_MSTOP(7, BIT(9))),
323 BUS_MSTOP(7, BIT(10))),
325 BUS_MSTOP(7, BIT(11))),
327 BUS_MSTOP(8, BIT(5)), 1),
329 BUS_MSTOP(8, BIT(5)), 1),
330 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
331 BUS_MSTOP(8, BIT(5)), 1),
333 BUS_MSTOP(8, BIT(5)), 1),
335 BUS_MSTOP(8, BIT(5))),
337 BUS_MSTOP(8, BIT(5))),
339 BUS_MSTOP(8, BIT(6)), 1),
341 BUS_MSTOP(8, BIT(6)), 1),
343 BUS_MSTOP(8, BIT(6)), 1),
345 BUS_MSTOP(8, BIT(6)), 1),
347 BUS_MSTOP(8, BIT(6))),
349 BUS_MSTOP(8, BIT(6))),
351 BUS_MSTOP(9, BIT(4))),
353 BUS_MSTOP(9, BIT(4))),
355 BUS_MSTOP(9, BIT(4))),
357 BUS_MSTOP(9, BIT(5))),
359 BUS_MSTOP(9, BIT(5))),
361 BUS_MSTOP(9, BIT(5))),
363 BUS_MSTOP(9, BIT(6))),
365 BUS_MSTOP(9, BIT(6))),
366 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
367 BUS_MSTOP(9, BIT(6))),
369 BUS_MSTOP(9, BIT(7))),
371 BUS_MSTOP(9, BIT(7))),
373 BUS_MSTOP(9, BIT(7))),
375 BUS_MSTOP(3, BIT(4))),
377 BUS_MSTOP(3, BIT(4))),
379 BUS_MSTOP(3, BIT(4))),
391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
414 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
421 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
422 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
423 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
424 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
425 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
426 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
427 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
428 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
429 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
430 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
438 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */