Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
73 {0, 1},
74 {1, 2},
82 {1, 4},
88 {1, 4},
96 {1, 4},
105 {1, 10},
134 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
135 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
136 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
137 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
144 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
146 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
149 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
150 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
151 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
152 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
154 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
161 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
162 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
175 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
184 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
185 DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
186 DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
188 CLK_PLLETH_DIV_125_FIX, 1, 1),
190 CLK_PLLETH_DIV_125_FIX, 1, 1),
191 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
197 BUS_MSTOP(5, BIT(9))),
198 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
208 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
222 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
231 BUS_MSTOP(1, BIT(0))),
233 BUS_MSTOP(1, BIT(0))),
238 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
249 BUS_MSTOP(11, BIT(1))),
251 BUS_MSTOP(11, BIT(1))),
252 DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
253 BUS_MSTOP(11, BIT(1))),
262 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
264 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
266 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
268 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
270 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
271 BUS_MSTOP(1, BIT(1))),
272 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
273 BUS_MSTOP(1, BIT(2))),
274 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
275 BUS_MSTOP(1, BIT(3))),
276 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
277 BUS_MSTOP(1, BIT(4))),
278 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
279 BUS_MSTOP(1, BIT(5))),
280 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
281 BUS_MSTOP(1, BIT(6))),
282 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
283 BUS_MSTOP(1, BIT(7))),
284 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
285 BUS_MSTOP(1, BIT(8))),
286 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
290 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
321 BUS_MSTOP(7, BIT(9))),
327 BUS_MSTOP(8, BIT(5)), 1),
328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
329 BUS_MSTOP(8, BIT(5)), 1),
331 BUS_MSTOP(8, BIT(5)), 1),
333 BUS_MSTOP(8, BIT(5)), 1),
339 BUS_MSTOP(8, BIT(6)), 1),
341 BUS_MSTOP(8, BIT(6)), 1),
343 BUS_MSTOP(8, BIT(6)), 1),
344 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
345 BUS_MSTOP(8, BIT(6)), 1),
351 BUS_MSTOP(9, BIT(4))),
353 BUS_MSTOP(9, BIT(4))),
355 BUS_MSTOP(9, BIT(4))),
357 BUS_MSTOP(9, BIT(5))),
359 BUS_MSTOP(9, BIT(5))),
361 BUS_MSTOP(9, BIT(5))),
363 BUS_MSTOP(9, BIT(6))),
364 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
365 BUS_MSTOP(9, BIT(6))),
367 BUS_MSTOP(9, BIT(6))),
369 BUS_MSTOP(9, BIT(7))),
371 BUS_MSTOP(9, BIT(7))),
373 BUS_MSTOP(9, BIT(7))),
376 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
383 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
384 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
385 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
386 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
387 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
388 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
389 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
390 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
395 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
396 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
403 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
410 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
411 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
412 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
413 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
414 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
417 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
418 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
419 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
420 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
426 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
431 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
432 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
437 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
444 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */