Lines Matching +full:1 +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
73 {0, 1},
74 {1, 2},
82 {1, 4},
88 {1, 4},
96 {1, 4},
105 {1, 10},
134 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
135 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
136 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
137 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
144 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
146 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
149 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
150 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
151 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
152 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
154 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
161 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
162 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
175 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
184 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
185 DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
186 DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
188 CLK_PLLETH_DIV_125_FIX, 1, 1),
190 CLK_PLLETH_DIV_125_FIX, 1, 1),
191 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
197 BUS_MSTOP(5, BIT(9))),
198 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
206 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
208 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
209 BUS_MSTOP(3, BIT(5))),
211 BUS_MSTOP(5, BIT(10))),
213 BUS_MSTOP(5, BIT(11))),
214 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
231 BUS_MSTOP(1, BIT(0))),
233 BUS_MSTOP(1, BIT(0))),
235 BUS_MSTOP(5, BIT(12))),
236 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
237 BUS_MSTOP(5, BIT(12))),
238 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
239 BUS_MSTOP(5, BIT(13))),
240 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
241 BUS_MSTOP(5, BIT(13))),
242 DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
244 DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
246 DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
248 DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
249 BUS_MSTOP(11, BIT(1))),
250 DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
251 BUS_MSTOP(11, BIT(1))),
252 DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
253 BUS_MSTOP(11, BIT(1))),
254 DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
256 DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
258 DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
264 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
271 BUS_MSTOP(1, BIT(1))),
272 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
273 BUS_MSTOP(1, BIT(2))),
275 BUS_MSTOP(1, BIT(3))),
277 BUS_MSTOP(1, BIT(4))),
279 BUS_MSTOP(1, BIT(5))),
281 BUS_MSTOP(1, BIT(6))),
283 BUS_MSTOP(1, BIT(7))),
285 BUS_MSTOP(1, BIT(8))),
287 BUS_MSTOP(4, BIT(5))),
288 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
289 BUS_MSTOP(4, BIT(5))),
290 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
291 BUS_MSTOP(4, BIT(5))),
292 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
294 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
296 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
298 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
302 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
306 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
308 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
310 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
312 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
314 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
316 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
318 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
320 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
322 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
324 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
326 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
327 BUS_MSTOP(8, BIT(5)), 1),
328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
329 BUS_MSTOP(8, BIT(5)), 1),
330 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
331 BUS_MSTOP(8, BIT(5)), 1),
332 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
333 BUS_MSTOP(8, BIT(5)), 1),
334 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
335 BUS_MSTOP(8, BIT(5))),
336 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
337 BUS_MSTOP(8, BIT(5))),
338 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
339 BUS_MSTOP(8, BIT(6)), 1),
340 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
341 BUS_MSTOP(8, BIT(6)), 1),
343 BUS_MSTOP(8, BIT(6)), 1),
344 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
345 BUS_MSTOP(8, BIT(6)), 1),
356 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
357 BUS_MSTOP(9, BIT(5))),
359 BUS_MSTOP(9, BIT(5))),
361 BUS_MSTOP(9, BIT(5))),
376 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
383 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
384 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
385 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
386 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
387 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
388 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
389 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
390 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
395 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
396 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
399 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
400 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
410 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
430 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
431 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
432 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
433 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
434 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
435 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
436 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
437 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
438 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
439 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
440 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
441 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
442 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
444 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */