Lines Matching +full:0 +full:x594
19 #define CPG_PL2SDHI_DSEL (0x218)
22 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
81 {0, 1},
85 {0, 0},
89 {0, 1},
94 {0, 0},
128 {0, 0},
133 {0, 16},
137 {0, 0},
162 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
215 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
217 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
245 0x514, 0, MSTOP(BUS_REG1, BIT(7))),
247 0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
249 0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
251 0x52c, 0, MSTOP(BUS_REG1, BIT(2))),
253 0x52c, 1, MSTOP(BUS_REG1, BIT(3))),
255 0x534, 0, MSTOP(BUS_REG0, BIT(4))),
257 0x534, 1, MSTOP(BUS_REG0, BIT(5))),
259 0x534, 2, MSTOP(BUS_REG0, BIT(6))),
261 0x538, 0, MSTOP(BUS_MCPU1, BIT(2))),
263 0x540, 0, MSTOP(BUS_MCPU1, BIT(4))),
265 0x544, 0, MSTOP(BUS_MCPU1, BIT(5))),
267 0x544, 1, MSTOP(BUS_MCPU1, BIT(6))),
269 0x544, 2, MSTOP(BUS_MCPU1, BIT(7))),
271 0x544, 3, MSTOP(BUS_MCPU1, BIT(8))),
273 0x548, 0, MSTOP(BUS_REG0, BIT(2))),
275 0x548, 1, MSTOP(BUS_REG0, BIT(2))),
277 0x548, 2, MSTOP(BUS_REG0, BIT(3))),
279 0x548, 3, MSTOP(BUS_REG0, BIT(3))),
281 0x550, 0, MSTOP(BUS_MCPU1, BIT(1))),
283 0x550, 1, MSTOP(BUS_MCPU1, BIT(1))),
285 0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))),
287 0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))),
289 0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))),
291 0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))),
293 0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))),
295 0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))),
297 0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))),
299 0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
301 0x558, 0, MSTOP(BUS_REG1, BIT(4))),
303 0x558, 1, 0),
305 0x558, 2, 0),
307 0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
309 0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
311 0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
313 0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
315 0x568, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
317 0x568, 1, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
319 0x568, 2, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
321 0x568, 3, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
323 0x568, 4, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
325 0x568, 5, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),
327 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
329 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
331 0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))),
333 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))),
335 0x570, 1, MSTOP(BUS_MCPU1, BIT(10))),
337 0x570, 2, MSTOP(BUS_MCPU1, BIT(11))),
339 0x570, 3, MSTOP(BUS_MCPU1, BIT(11))),
341 0x570, 4, MSTOP(BUS_MCPU1, BIT(12))),
343 0x570, 5, MSTOP(BUS_MCPU1, BIT(12))),
345 0x570, 6, MSTOP(BUS_MCPU1, BIT(13))),
347 0x570, 7, MSTOP(BUS_MCPU1, BIT(13))),
349 0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))),
351 0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))),
353 0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))),
355 0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))),
357 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
359 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
361 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
363 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
365 0x580, 0, MSTOP(BUS_MCPU2, BIT(10))),
367 0x580, 1, MSTOP(BUS_MCPU2, BIT(11))),
369 0x580, 2, MSTOP(BUS_MCPU2, BIT(12))),
371 0x580, 3, MSTOP(BUS_MCPU2, BIT(13))),
373 0x584, 0, MSTOP(BUS_MCPU2, BIT(1))),
375 0x584, 1, MSTOP(BUS_MCPU2, BIT(2))),
377 0x584, 2, MSTOP(BUS_MCPU2, BIT(3))),
379 0x584, 3, MSTOP(BUS_MCPU2, BIT(4))),
381 0x584, 4, MSTOP(BUS_MCPU2, BIT(5))),
383 0x588, 0, MSTOP(BUS_MCPU2, BIT(7))),
385 0x588, 1, MSTOP(BUS_MCPU2, BIT(8))),
387 0x590, 0, MSTOP(BUS_MCPU1, BIT(14))),
389 0x590, 1, MSTOP(BUS_MCPU1, BIT(15))),
391 0x590, 2, MSTOP(BUS_MCPU2, BIT(0))),
393 0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
395 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))),
397 0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
399 0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))),
401 0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))),
406 0x5e8, 0, 0),
408 0x5e8, 1, 0),
410 0x5e8, 2, 0),
412 0x5e8, 3, 0),
414 0x5e8, 4, 0),
420 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
421 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
422 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
423 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
424 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
425 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
426 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
427 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
428 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
429 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
430 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
431 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
432 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
433 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
434 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
435 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
436 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
437 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
438 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
439 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
440 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
441 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
442 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
443 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
444 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
445 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
446 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
447 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
448 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
449 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
450 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
451 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
452 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
453 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
454 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
455 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
456 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
457 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
458 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
459 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
460 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
461 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
462 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
463 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
464 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
465 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
466 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
467 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
468 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
469 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
470 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
471 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
472 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
473 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
474 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
475 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
476 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
477 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
478 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
479 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
480 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
482 DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0),