Lines Matching +full:0 +full:x584
19 #define CPG_PL2SDHI_DSEL (0x218)
22 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
81 {0, 1},
85 {0, 0},
89 {0, 1},
94 {0, 0},
98 {0, 16},
102 {0, 0},
117 struct cpg_core_clk drp[0];
127 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
180 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
182 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
202 struct rzg2l_mod_clk drp[0];
207 0x514, 0),
209 0x518, 0),
211 0x518, 1),
213 0x52c, 0),
215 0x52c, 1),
217 0x534, 0),
219 0x534, 1),
221 0x534, 2),
223 0x538, 0),
225 0x540, 0),
227 0x544, 0),
229 0x544, 1),
231 0x544, 2),
233 0x544, 3),
235 0x548, 0),
237 0x548, 1),
239 0x548, 2),
241 0x548, 3),
243 0x550, 0),
245 0x550, 1),
247 0x554, 0),
249 0x554, 1),
251 0x554, 2),
253 0x554, 3),
255 0x554, 4),
257 0x554, 5),
259 0x554, 6),
261 0x554, 7),
263 0x558, 0),
265 0x558, 1),
267 0x558, 2),
269 0x564, 0),
271 0x564, 1),
273 0x564, 2),
275 0x564, 3),
277 0x568, 0),
279 0x568, 1),
281 0x568, 2),
283 0x568, 3),
285 0x568, 4),
287 0x568, 5),
289 0x56c, 0),
291 0x56c, 0),
293 0x56c, 1),
295 0x570, 0),
297 0x570, 1),
299 0x570, 2),
301 0x570, 3),
303 0x570, 4),
305 0x570, 5),
307 0x570, 6),
309 0x570, 7),
311 0x578, 0),
313 0x578, 1),
315 0x578, 2),
317 0x578, 3),
319 0x57c, 0),
321 0x57c, 0),
323 0x57c, 1),
325 0x57c, 1),
327 0x580, 0),
329 0x580, 1),
331 0x580, 2),
333 0x580, 3),
335 0x584, 0),
337 0x584, 1),
339 0x584, 2),
341 0x584, 3),
343 0x584, 4),
345 0x588, 0),
347 0x588, 1),
349 0x590, 0),
351 0x590, 1),
353 0x590, 2),
355 0x594, 0),
357 0x598, 0),
359 0x5a8, 0),
361 0x5a8, 1),
363 0x5ac, 0),
372 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
373 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
374 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
375 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
376 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
377 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
378 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
379 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
380 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
381 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
382 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
383 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
384 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
385 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
386 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
387 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
388 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
389 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
390 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
391 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
392 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
393 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
394 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
395 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
396 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
397 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
398 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
399 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
400 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
401 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
402 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
403 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
404 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
405 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
406 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
407 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
408 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
409 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
410 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
411 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
412 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
413 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
414 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
415 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
416 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
417 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
418 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
419 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
420 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
421 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
422 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
423 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
424 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
425 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
426 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
427 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
428 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
429 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
430 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
431 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
432 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),