Lines Matching +full:0 +full:x594
18 #define CPG_PL2SDHI_DSEL (0x218)
21 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
74 {0, 1},
78 {0, 0},
82 {0, 1},
87 {0, 0},
106 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
151 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
153 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
167 0x514, 0, MSTOP(BUS_REG1, BIT(7))),
169 0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
171 0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
175 0x518, 0, MSTOP(BUS_PERI_CPU, BIT(13))),
177 0x518, 1, MSTOP(BUS_PERI_CPU, BIT(13))),
180 0x52c, 0, MSTOP(BUS_REG1, BIT(2))),
182 0x52c, 1, MSTOP(BUS_REG1, BIT(3))),
184 0x534, 0, MSTOP(BUS_REG0, BIT(4))),
186 0x534, 1, MSTOP(BUS_REG0, BIT(5))),
188 0x534, 2, MSTOP(BUS_REG0, BIT(6))),
190 0x538, 0, MSTOP(BUS_MCPU1, BIT(2))),
192 0x548, 0, MSTOP(BUS_REG0, BIT(2))),
194 0x548, 1, MSTOP(BUS_REG0, BIT(2))),
196 0x550, 0, MSTOP(BUS_MCPU1, BIT(1))),
198 0x550, 1, MSTOP(BUS_MCPU1, BIT(1))),
200 0x554, 0, MSTOP(BUS_PERI_COM, BIT(0))),
202 0x554, 1, MSTOP(BUS_PERI_COM, BIT(0))),
204 0x554, 2, MSTOP(BUS_PERI_COM, BIT(0))),
206 0x554, 3, MSTOP(BUS_PERI_COM, BIT(0))),
208 0x554, 4, MSTOP(BUS_PERI_COM, BIT(1))),
210 0x554, 5, MSTOP(BUS_PERI_COM, BIT(1))),
212 0x554, 6, MSTOP(BUS_PERI_COM, BIT(1))),
214 0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
217 0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
219 0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
221 0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
223 0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
225 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
227 0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),
229 0x56c, 1, MSTOP(BUS_PERI_VIDEO, BIT(9))),
232 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))),
234 0x570, 1, MSTOP(BUS_MCPU1, BIT(10))),
236 0x570, 2, MSTOP(BUS_MCPU1, BIT(11))),
238 0x570, 3, MSTOP(BUS_MCPU1, BIT(11))),
240 0x570, 4, MSTOP(BUS_MCPU1, BIT(12))),
242 0x570, 5, MSTOP(BUS_MCPU1, BIT(12))),
244 0x570, 6, MSTOP(BUS_MCPU1, BIT(13))),
246 0x570, 7, MSTOP(BUS_MCPU1, BIT(13))),
248 0x578, 0, MSTOP(BUS_PERI_COM, BIT(5))),
250 0x578, 1, MSTOP(BUS_PERI_COM, BIT(7))),
252 0x578, 2, MSTOP(BUS_PERI_COM, BIT(6))),
254 0x578, 3, MSTOP(BUS_PERI_COM, BIT(4))),
256 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
258 0x57c, 0, MSTOP(BUS_PERI_COM, BIT(2))),
260 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
262 0x57c, 1, MSTOP(BUS_PERI_COM, BIT(3))),
264 0x580, 0, MSTOP(BUS_MCPU2, BIT(10))),
266 0x580, 1, MSTOP(BUS_MCPU2, BIT(11))),
268 0x580, 2, MSTOP(BUS_MCPU2, BIT(12))),
270 0x580, 3, MSTOP(BUS_MCPU2, BIT(13))),
272 0x584, 0, MSTOP(BUS_MCPU2, BIT(1))),
274 0x584, 1, MSTOP(BUS_MCPU2, BIT(2))),
276 0x584, 2, MSTOP(BUS_MCPU2, BIT(3))),
278 0x584, 3, MSTOP(BUS_MCPU2, BIT(4))),
280 0x584, 4, MSTOP(BUS_MCPU2, BIT(5))),
282 0x588, 0, MSTOP(BUS_MCPU2, BIT(7))),
284 0x588, 1, MSTOP(BUS_MCPU2, BIT(8))),
286 0x590, 0, MSTOP(BUS_MCPU1, BIT(14))),
288 0x590, 1, MSTOP(BUS_MCPU1, BIT(15))),
290 0x590, 2, MSTOP(BUS_MCPU2, BIT(0))),
292 0x594, 0, MSTOP(BUS_MCPU2, BIT(9))),
294 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))),
296 0x5a8, 0, MSTOP(BUS_MCPU2, BIT(14))),
298 0x5a8, 1, MSTOP(BUS_MCPU2, BIT(14))),
300 0x5ac, 0, MSTOP(BUS_MCPU2, BIT(15))),
303 0x608, 0, MSTOP(BUS_REG1, BIT(7))),
309 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
310 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
311 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
314 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
316 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
317 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
318 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
319 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
320 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
321 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
322 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
323 DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
324 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
325 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
327 DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0),
328 DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1),
329 DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2),
330 DEF_RST(R9A07G043_LCDC_RESET_N, 0x86c, 0),
332 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
333 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
334 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
335 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
336 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
337 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
338 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
339 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
340 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
341 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
342 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
343 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
344 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
345 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
346 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
347 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
348 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
349 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
350 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
351 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
352 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
353 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
354 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
355 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
356 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
357 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
358 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
359 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
360 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
361 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
362 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
363 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
365 DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),