Lines Matching +full:0 +full:x584
18 #define CPG_PL2SDHI_DSEL (0x218)
21 #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
74 {0, 1},
78 {0, 0},
82 {0, 1},
87 {0, 0},
104 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
144 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
146 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
160 0x514, 0),
162 0x518, 0),
164 0x518, 1),
168 0x518, 0),
170 0x518, 1),
173 0x52c, 0),
175 0x52c, 1),
177 0x534, 0),
179 0x534, 1),
181 0x534, 2),
183 0x538, 0),
185 0x548, 0),
187 0x548, 1),
189 0x550, 0),
191 0x550, 1),
193 0x554, 0),
195 0x554, 1),
197 0x554, 2),
199 0x554, 3),
201 0x554, 4),
203 0x554, 5),
205 0x554, 6),
207 0x554, 7),
210 0x564, 0),
212 0x564, 1),
214 0x564, 2),
216 0x564, 3),
218 0x56c, 0),
220 0x56c, 0),
222 0x56c, 1),
225 0x570, 0),
227 0x570, 1),
229 0x570, 2),
231 0x570, 3),
233 0x570, 4),
235 0x570, 5),
237 0x570, 6),
239 0x570, 7),
241 0x578, 0),
243 0x578, 1),
245 0x578, 2),
247 0x578, 3),
249 0x57c, 0),
251 0x57c, 0),
253 0x57c, 1),
255 0x57c, 1),
257 0x580, 0),
259 0x580, 1),
261 0x580, 2),
263 0x580, 3),
265 0x584, 0),
267 0x584, 1),
269 0x584, 2),
271 0x584, 3),
273 0x584, 4),
275 0x588, 0),
277 0x588, 1),
279 0x590, 0),
281 0x590, 1),
283 0x590, 2),
285 0x594, 0),
287 0x598, 0),
289 0x5a8, 0),
291 0x5a8, 1),
293 0x5ac, 0),
296 0x608, 0),
302 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
303 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
304 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
307 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
309 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
310 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
311 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
312 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
313 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
314 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
315 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
316 DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
317 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
318 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
320 DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0),
321 DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1),
322 DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2),
323 DEF_RST(R9A07G043_LCDC_RESET_N, 0x86c, 0),
325 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
326 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
327 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
328 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
329 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
330 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
331 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
332 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
333 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
334 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
335 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
336 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
337 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
338 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
339 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
340 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
341 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
342 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
343 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
344 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
345 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
346 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
347 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
348 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
349 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
350 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
351 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
352 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
353 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
354 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
355 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
356 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
358 DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),