Lines Matching +full:0 +full:x160
24 #define CPG_SD0CKCR 0x0074
52 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
54 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
60 { 0, 0 },
101 DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
102 DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
103 DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
180 * 0 0 0 16.66 x 1 x192 x192 x96
181 * 0 0 1 16.66 x 1 x192 x192 x80
182 * 0 1 0 20 x 1 x160 x160 x80
183 * 0 1 1 20 x 1 x160 x160 x66
184 * 1 0 0 27 / 2 x236 x236 x118
185 * 1 0 1 27 / 2 x236 x236 x98
186 * 1 1 0 33.33 / 2 x192 x192 x96
248 __clk_get_name(parent), 0, in r8a77970_cpg_clk_register()
250 shift, 4, 0, table, &cpg_lock); in r8a77970_cpg_clk_register()