Lines Matching +full:0 +full:x160

97 	DEF_GEN3_SDH("sd0h",    R8A774B1_CLK_SD0H,  CLK_SDSRC,         0x074),
98 	DEF_GEN3_SDH("sd1h",    R8A774B1_CLK_SD1H,  CLK_SDSRC,         0x078),
99 	DEF_GEN3_SDH("sd2h",    R8A774B1_CLK_SD2H,  CLK_SDSRC,         0x268),
100 	DEF_GEN3_SDH("sd3h",    R8A774B1_CLK_SD3H,  CLK_SDSRC,         0x26c),
101 	DEF_GEN3_SD("sd0",      R8A774B1_CLK_SD0,   R8A774B1_CLK_SD0H, 0x074),
102 	DEF_GEN3_SD("sd1",      R8A774B1_CLK_SD1,   R8A774B1_CLK_SD1H, 0x078),
103 	DEF_GEN3_SD("sd2",      R8A774B1_CLK_SD2,   R8A774B1_CLK_SD2H, 0x268),
104 	DEF_GEN3_SD("sd3",      R8A774B1_CLK_SD3,   R8A774B1_CLK_SD3H, 0x26c),
113 	DEF_DIV6P1("canfd",     R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 	DEF_DIV6P1("csi0",      R8A774B1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
115 	DEF_DIV6P1("mso",       R8A774B1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
116 	DEF_DIV6P1("hdmi",      R8A774B1_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
130 	DEF_MOD("fdp1-0",		 119,	R8A774B1_CLK_S0D1),
262  * 0  0  0  0	16.66 x 1	x180	x192	x192	x144	/16
263  * 0  0  0  1	16.66 x 1	x180	x192	x128	x144	/16
264  * 0  0  1  0	Prohibited setting
265  * 0  0  1  1	16.66 x 1	x180	x192	x192	x144	/16
266  * 0  1  0  0	20    x 1	x150	x160	x160	x120	/19
267  * 0  1  0  1	20    x 1	x150	x160	x106	x120	/19
268  * 0  1  1  0	Prohibited setting
269  * 0  1  1  1	20    x 1	x150	x160	x160	x120	/19
270  * 1  0  0  0	25    x 1	x120	x128	x128	x96	/24
271  * 1  0  0  1	25    x 1	x120	x128	x84	x96	/24
272  * 1  0  1  0	Prohibited setting
273  * 1  0  1  1	25    x 1	x120	x128	x128	x96	/24
274  * 1  1  0  0	33.33 / 2	x180	x192	x192	x144	/32
275  * 1  1  0  1	33.33 / 2	x180	x192	x128	x144	/32
276  * 1  1  1  0	Prohibited setting
288 	{ 0, /* Prohibited setting */				},
292 	{ 0, /* Prohibited setting */				},
296 	{ 0, /* Prohibited setting */				},
300 	{ 0, /* Prohibited setting */				},
316 		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);  in r8a774b1_cpg_mssr_init()