Lines Matching +full:clock +full:- +full:skip

1 // SPDX-License-Identifier: GPL-2.0
6  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <linux/clk-provider.h>
26 /* -----------------------------------------------------------------------------
63 	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */  in rz_cpg_register_clock()
65 		return ERR_PTR(-ENXIO);  in rz_cpg_register_clock()
67 	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)  in rz_cpg_register_clock()
76 		return ERR_PTR(-EINVAL);  in rz_cpg_register_clock()
90 	num_clks = of_property_count_strings(np, "clock-output-names");  in rz_cpg_clocks_init()
98 	data->clks = clks;  in rz_cpg_clocks_init()
99 	data->clk_num = num_clks;  in rz_cpg_clocks_init()
107 		of_property_read_string_index(np, "clock-output-names", i, &name);  in rz_cpg_clocks_init()
111 			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",  in rz_cpg_clocks_init()
114 			data->clks[i] = clk;  in rz_cpg_clocks_init()
121 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);