Lines Matching +full:re +full:- +full:configurable
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
90 /* PLLC0/1 are configurable multiplier clocks. Register them as in r8a7740_cpg_register_clock()
118 for (c = div4_clks; c->name; c++) { in r8a7740_cpg_register_clock()
119 if (!strcmp(name, c->name)) { in r8a7740_cpg_register_clock()
122 reg = c->reg; in r8a7740_cpg_register_clock()
123 shift = c->shift; in r8a7740_cpg_register_clock()
127 if (!c->name) in r8a7740_cpg_register_clock()
128 return ERR_PTR(-EINVAL); in r8a7740_cpg_register_clock()
137 table, &cpg->lock); in r8a7740_cpg_register_clock()
152 num_clks = of_property_count_strings(np, "clock-output-names"); in r8a7740_cpg_clocks_init()
161 /* We're leaking memory on purpose, there's no point in cleaning in r8a7740_cpg_clocks_init()
167 spin_lock_init(&cpg->lock); in r8a7740_cpg_clocks_init()
169 cpg->data.clks = clks; in r8a7740_cpg_clocks_init()
170 cpg->data.clk_num = num_clks; in r8a7740_cpg_clocks_init()
180 of_property_read_string_index(np, "clock-output-names", i, in r8a7740_cpg_clocks_init()
188 cpg->data.clks[i] = clk; in r8a7740_cpg_clocks_init()
191 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); in r8a7740_cpg_clocks_init()
193 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",