Lines Matching +full:0 +full:x8004
28 { 249600000, 2000000000, 0 },
33 .l = 0x14,
34 .alpha = 0xD555,
35 .config_ctl_val = 0x20485699,
36 .config_ctl_hi_val = 0x00002261,
37 .config_ctl_hi1_val = 0x329A299C,
38 .user_ctl_val = 0x00000001,
39 .user_ctl_hi_val = 0x00000805,
40 .user_ctl_hi1_val = 0x00000000,
44 .offset = 0x0,
61 { P_BI_TCXO, 0 },
71 { P_SLEEP_CLK, 0 },
79 F(133333333, P_VIDEO_PLL0_OUT_EVEN, 3, 0, 0),
80 F(240000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
81 F(335000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
82 F(424000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
83 F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
88 .cmd_rcgr = 0x1000,
89 .mnd_width = 0,
103 F(32000, P_SLEEP_CLK, 1, 0, 0),
108 .cmd_rcgr = 0x701c,
109 .mnd_width = 0,
122 .halt_reg = 0x5004,
125 .enable_reg = 0x5004,
126 .enable_mask = BIT(0),
140 .halt_reg = 0x800c,
143 .enable_reg = 0x800c,
144 .enable_mask = BIT(0),
153 .halt_reg = 0x3010,
155 .hwcg_reg = 0x3010,
158 .enable_reg = 0x3010,
159 .enable_mask = BIT(0),
173 .halt_reg = 0x2014,
176 .enable_reg = 0x2014,
177 .enable_mask = BIT(0),
191 .halt_reg = 0x8004,
194 .enable_reg = 0x8004,
195 .enable_mask = BIT(0),
204 .halt_reg = 0x7034,
207 .enable_reg = 0x7034,
208 .enable_mask = BIT(0),
222 .halt_reg = 0x801c,
225 .enable_reg = 0x801c,
226 .enable_mask = BIT(0),
235 .gdscr = 0x3004,
236 .en_rest_wait_val = 0x2,
237 .en_few_wait_val = 0x2,
238 .clk_dis_wait_val = 0x6,
247 .gdscr = 0x2004,
248 .en_rest_wait_val = 0x2,
249 .en_few_wait_val = 0x2,
250 .clk_dis_wait_val = 0x6,
280 .max_register = 0xb000,