Lines Matching +full:0 +full:x104c
48 { 0x0, 1 },
49 { 0x1, 2 },
50 { 0x3, 4 },
51 { 0x7, 8 },
56 .offset = 0xc000,
59 .enable_reg = 0x1e0,
60 .enable_mask = BIT(0),
73 .offset = 0xc000,
88 .offset = 0xc050,
91 .enable_reg = 0x1e0,
105 .offset = 0xc050,
120 .offset = 0x0,
133 .offset = 0x0,
148 .offset = 0x50,
161 .offset = 0x50,
176 .offset = 0xa0,
189 .offset = 0xa0,
204 .offset = 0xf0,
217 .offset = 0xf0,
232 .offset = 0x140,
245 .offset = 0x140,
260 .offset = 0x190,
273 .offset = 0x190,
288 { P_XO, 0 },
298 { P_XO, 0 },
310 { P_XO, 0 },
322 { P_XO, 0 },
334 { P_XO, 0 },
346 { P_XO, 0 },
360 { P_XO, 0 },
376 { P_XO, 0 },
392 { P_XO, 0 },
410 { P_XO, 0 },
428 { P_XO, 0 },
446 { P_XO, 0 },
466 .cmd_rcgr = 0x2120,
479 .cmd_rcgr = 0x2140,
492 F(37500000, P_GPLL0, 16, 0, 0),
493 F(50000000, P_GPLL0, 12, 0, 0),
494 F(100000000, P_GPLL0, 6, 0, 0),
499 .cmd_rcgr = 0x3300,
512 F(100000000, P_GPLL0, 6, 0, 0),
513 F(200000000, P_GPLL0, 3, 0, 0),
514 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
515 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
516 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
517 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
518 F(600000000, P_GPLL0, 1, 0, 0),
523 .cmd_rcgr = 0x3640,
536 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
537 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
538 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
539 F(300000000, P_GPLL0, 2, 0, 0),
540 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
541 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
546 .cmd_rcgr = 0x3090,
559 .cmd_rcgr = 0x3100,
572 .cmd_rcgr = 0x3160,
585 .cmd_rcgr = 0x31c0,
598 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
599 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
600 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
601 F(300000000, P_GPLL0, 2, 0, 0),
602 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
607 .cmd_rcgr = 0x3800,
620 F(200000000, P_GPLL0, 3, 0, 0),
621 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
626 .cmd_rcgr = 0x3000,
639 .cmd_rcgr = 0x3030,
652 .cmd_rcgr = 0x3060,
665 F(19200000, P_XO, 1, 0, 0),
670 .cmd_rcgr = 0x2260,
690 .cmd_rcgr = 0x2220,
703 F(162000, P_DPLINK, 2, 0, 0),
704 F(270000, P_DPLINK, 2, 0, 0),
705 F(540000, P_DPLINK, 2, 0, 0),
710 .cmd_rcgr = 0x2200,
723 F(154000000, P_DPVCO, 1, 0, 0),
724 F(337500000, P_DPVCO, 2, 0, 0),
725 F(675000000, P_DPVCO, 2, 0, 0),
730 .cmd_rcgr = 0x2240,
743 F(19200000, P_XO, 1, 0, 0),
748 .cmd_rcgr = 0x2160,
761 .cmd_rcgr = 0x2180,
779 .cmd_rcgr = 0x2060,
793 F(100000000, P_GPLL0, 6, 0, 0),
794 F(200000000, P_GPLL0, 3, 0, 0),
795 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
796 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
797 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
802 .cmd_rcgr = 0x3b00,
815 F(19200000, P_XO, 1, 0, 0),
820 .cmd_rcgr = 0x2100,
833 F(75000000, P_GPLL0, 8, 0, 0),
834 F(150000000, P_GPLL0, 4, 0, 0),
835 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
836 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
841 .cmd_rcgr = 0x3500,
854 F(19200000, P_XO, 1, 0, 0),
855 F(75000000, P_GPLL0_DIV, 4, 0, 0),
856 F(171428571, P_GPLL0, 3.5, 0, 0),
857 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
858 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
863 .cmd_rcgr = 0xf020,
876 F(4800000, P_XO, 4, 0, 0),
879 F(9600000, P_XO, 2, 0, 0),
881 F(19200000, P_XO, 1, 0, 0),
890 .cmd_rcgr = 0x3360,
903 .cmd_rcgr = 0x3390,
916 .cmd_rcgr = 0x33c0,
929 .cmd_rcgr = 0x33f0,
942 F(85714286, P_GPLL0, 7, 0, 0),
943 F(100000000, P_GPLL0, 6, 0, 0),
944 F(150000000, P_GPLL0, 4, 0, 0),
945 F(171428571, P_GPLL0, 3.5, 0, 0),
946 F(200000000, P_GPLL0, 3, 0, 0),
947 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
948 F(300000000, P_GPLL0, 2, 0, 0),
949 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
950 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
955 .cmd_rcgr = 0x2040,
968 F(19200000, P_XO, 1, 0, 0),
973 .cmd_rcgr = 0x2080,
986 F(19200000, P_XO, 1, 0, 0),
987 F(40000000, P_GPLL0, 15, 0, 0),
988 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
993 .cmd_rcgr = 0x5000,
1006 F(75000000, P_GPLL0, 8, 0, 0),
1007 F(171428571, P_GPLL0, 3.5, 0, 0),
1008 F(240000000, P_GPLL0, 2.5, 0, 0),
1009 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1010 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1016 .cmd_rcgr = 0xd000,
1029 .cmd_rcgr = 0x2000,
1043 .cmd_rcgr = 0x2020,
1057 F(171428571, P_GPLL0, 3.5, 0, 0),
1058 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1059 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1060 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1065 .cmd_rcgr = 0x21a0,
1078 F(200000000, P_GPLL0, 3, 0, 0),
1079 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1080 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1081 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1082 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1087 .cmd_rcgr = 0x1000,
1100 .cmd_rcgr = 0x1060,
1113 .cmd_rcgr = 0x1080,
1126 F(200000000, P_GPLL0, 3, 0, 0),
1127 F(300000000, P_GPLL0, 2, 0, 0),
1128 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1129 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1130 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1131 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1132 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1133 F(600000000, P_GPLL0, 1, 0, 0),
1138 .cmd_rcgr = 0x3600,
1151 .cmd_rcgr = 0x3620,
1164 .halt_reg = 0x328,
1165 .hwcg_reg = 0x328,
1168 .enable_reg = 0x328,
1169 .enable_mask = BIT(0),
1181 .halt_reg = 0x1028,
1183 .enable_reg = 0x1028,
1184 .enable_mask = BIT(0),
1196 .halt_reg = 0x1030,
1197 .hwcg_reg = 0x1030,
1200 .enable_reg = 0x1030,
1201 .enable_mask = BIT(0),
1213 .halt_reg = 0x1034,
1215 .enable_reg = 0x1034,
1216 .enable_mask = BIT(0),
1227 .halt_reg = 0x1038,
1229 .enable_reg = 0x1038,
1230 .enable_mask = BIT(0),
1242 .halt_reg = 0x1048,
1244 .enable_reg = 0x1048,
1245 .enable_mask = BIT(0),
1257 .halt_reg = 0x104c,
1259 .enable_reg = 0x104c,
1260 .enable_mask = BIT(0),
1272 .halt_reg = 0x2308,
1273 .hwcg_reg = 0x2308,
1276 .enable_reg = 0x2308,
1277 .enable_mask = BIT(0),
1289 .halt_reg = 0x230c,
1291 .enable_reg = 0x230c,
1292 .enable_mask = BIT(0),
1304 .halt_reg = 0x2310,
1306 .enable_reg = 0x2310,
1307 .enable_mask = BIT(0),
1318 .halt_reg = 0x2314,
1320 .enable_reg = 0x2314,
1321 .enable_mask = BIT(0),
1333 .halt_reg = 0x2318,
1335 .enable_reg = 0x2318,
1336 .enable_mask = BIT(0),
1348 .halt_reg = 0x231c,
1350 .enable_reg = 0x231c,
1351 .enable_mask = BIT(0),
1363 .halt_reg = 0x2320,
1365 .enable_reg = 0x2320,
1366 .enable_mask = BIT(0),
1378 .halt_reg = 0x2324,
1380 .enable_reg = 0x2324,
1381 .enable_mask = BIT(0),
1393 .halt_reg = 0x2328,
1395 .enable_reg = 0x2328,
1396 .enable_mask = BIT(0),
1408 .halt_reg = 0x2338,
1410 .enable_reg = 0x2338,
1411 .enable_mask = BIT(0),
1423 .halt_reg = 0x233c,
1425 .enable_reg = 0x233c,
1426 .enable_mask = BIT(0),
1438 .halt_reg = 0x2340,
1440 .enable_reg = 0x2340,
1441 .enable_mask = BIT(0),
1453 .halt_reg = 0x2344,
1455 .enable_reg = 0x2344,
1456 .enable_mask = BIT(0),
1468 .halt_reg = 0x2348,
1470 .enable_reg = 0x2348,
1471 .enable_mask = BIT(0),
1483 .halt_reg = 0x2350,
1485 .enable_reg = 0x2350,
1486 .enable_mask = BIT(0),
1498 .halt_reg = 0x2354,
1500 .enable_reg = 0x2354,
1501 .enable_mask = BIT(0),
1513 .halt_reg = 0x2358,
1515 .enable_reg = 0x2358,
1516 .enable_mask = BIT(0),
1528 .halt_reg = 0x235c,
1530 .enable_reg = 0x235c,
1531 .enable_mask = BIT(0),
1543 .halt_reg = 0x2360,
1545 .enable_reg = 0x2360,
1546 .enable_mask = BIT(0),
1558 .halt_reg = 0x2364,
1560 .enable_reg = 0x2364,
1561 .enable_mask = BIT(0),
1573 .halt_reg = 0x2374,
1575 .enable_reg = 0x2374,
1576 .enable_mask = BIT(0),
1588 .halt_reg = 0x2378,
1590 .enable_reg = 0x2378,
1591 .enable_mask = BIT(0),
1603 .halt_reg = 0x3024,
1605 .enable_reg = 0x3024,
1606 .enable_mask = BIT(0),
1618 .halt_reg = 0x3054,
1620 .enable_reg = 0x3054,
1621 .enable_mask = BIT(0),
1633 .halt_reg = 0x3084,
1635 .enable_reg = 0x3084,
1636 .enable_mask = BIT(0),
1648 .halt_reg = 0x30b4,
1650 .enable_reg = 0x30b4,
1651 .enable_mask = BIT(0),
1663 .halt_reg = 0x30bc,
1665 .enable_reg = 0x30bc,
1666 .enable_mask = BIT(0),
1678 .halt_reg = 0x30d4,
1680 .enable_reg = 0x30d4,
1681 .enable_mask = BIT(0),
1693 .halt_reg = 0x30e4,
1695 .enable_reg = 0x30e4,
1696 .enable_mask = BIT(0),
1708 .halt_reg = 0x3124,
1710 .enable_reg = 0x3124,
1711 .enable_mask = BIT(0),
1723 .halt_reg = 0x3128,
1725 .enable_reg = 0x3128,
1726 .enable_mask = BIT(0),
1738 .halt_reg = 0x3144,
1740 .enable_reg = 0x3144,
1741 .enable_mask = BIT(0),
1753 .halt_reg = 0x3154,
1755 .enable_reg = 0x3154,
1756 .enable_mask = BIT(0),
1768 .halt_reg = 0x3184,
1770 .enable_reg = 0x3184,
1771 .enable_mask = BIT(0),
1783 .halt_reg = 0x3188,
1785 .enable_reg = 0x3188,
1786 .enable_mask = BIT(0),
1798 .halt_reg = 0x31a4,
1800 .enable_reg = 0x31a4,
1801 .enable_mask = BIT(0),
1813 .halt_reg = 0x31b4,
1815 .enable_reg = 0x31b4,
1816 .enable_mask = BIT(0),
1828 .halt_reg = 0x31e4,
1830 .enable_reg = 0x31e4,
1831 .enable_mask = BIT(0),
1843 .halt_reg = 0x31e8,
1845 .enable_reg = 0x31e8,
1846 .enable_mask = BIT(0),
1858 .halt_reg = 0x3204,
1860 .enable_reg = 0x3204,
1861 .enable_mask = BIT(0),
1873 .halt_reg = 0x3214,
1875 .enable_reg = 0x3214,
1876 .enable_mask = BIT(0),
1888 .halt_reg = 0x3224,
1890 .enable_reg = 0x3224,
1891 .enable_mask = BIT(0),
1903 .halt_reg = 0x3344,
1905 .enable_reg = 0x3344,
1906 .enable_mask = BIT(0),
1918 .halt_reg = 0x3348,
1920 .enable_reg = 0x3348,
1921 .enable_mask = BIT(0),
1933 .halt_reg = 0x3384,
1935 .enable_reg = 0x3384,
1936 .enable_mask = BIT(0),
1948 .halt_reg = 0x33b4,
1950 .enable_reg = 0x33b4,
1951 .enable_mask = BIT(0),
1963 .halt_reg = 0x33e4,
1965 .enable_reg = 0x33e4,
1966 .enable_mask = BIT(0),
1978 .halt_reg = 0x3414,
1980 .enable_reg = 0x3414,
1981 .enable_mask = BIT(0),
1993 .halt_reg = 0x3484,
1995 .enable_reg = 0x3484,
1996 .enable_mask = BIT(0),
2008 .halt_reg = 0x348c,
2010 .enable_reg = 0x348c,
2011 .enable_mask = BIT(0),
2023 .halt_reg = 0x3494,
2025 .enable_reg = 0x3494,
2026 .enable_mask = BIT(0),
2038 .halt_reg = 0x35a8,
2040 .enable_reg = 0x35a8,
2041 .enable_mask = BIT(0),
2053 .halt_reg = 0x35b4,
2055 .enable_reg = 0x35b4,
2056 .enable_mask = BIT(0),
2068 .halt_reg = 0x35b8,
2070 .enable_reg = 0x35b8,
2071 .enable_mask = BIT(0),
2082 .halt_reg = 0x3668,
2084 .enable_reg = 0x3668,
2085 .enable_mask = BIT(0),
2097 .halt_reg = 0x3678,
2099 .enable_reg = 0x3678,
2100 .enable_mask = BIT(0),
2112 .halt_reg = 0x36a8,
2114 .enable_reg = 0x36a8,
2115 .enable_mask = BIT(0),
2127 .halt_reg = 0x36ac,
2129 .enable_reg = 0x36ac,
2130 .enable_mask = BIT(0),
2142 .halt_reg = 0x36b0,
2144 .enable_reg = 0x36b0,
2145 .enable_mask = BIT(0),
2157 .halt_reg = 0x36b4,
2159 .enable_reg = 0x36b4,
2160 .enable_mask = BIT(0),
2172 .halt_reg = 0x36b8,
2174 .enable_reg = 0x36b8,
2175 .enable_mask = BIT(0),
2187 .halt_reg = 0x36bc,
2189 .enable_reg = 0x36bc,
2190 .enable_mask = BIT(0),
2201 .halt_reg = 0x36c4,
2203 .enable_reg = 0x36c4,
2204 .enable_mask = BIT(0),
2215 .halt_reg = 0x36c8,
2217 .enable_reg = 0x36c8,
2218 .enable_mask = BIT(0),
2230 .halt_reg = 0x3704,
2232 .enable_reg = 0x3704,
2233 .enable_mask = BIT(0),
2245 .halt_reg = 0x3714,
2247 .enable_reg = 0x3714,
2248 .enable_mask = BIT(0),
2260 .halt_reg = 0x3720,
2262 .enable_reg = 0x3720,
2263 .enable_mask = BIT(0),
2275 .halt_reg = 0x3724,
2277 .enable_reg = 0x3724,
2278 .enable_mask = BIT(0),
2290 .halt_reg = 0x3730,
2292 .enable_reg = 0x3730,
2293 .enable_mask = BIT(0),
2305 .halt_reg = 0x3734,
2307 .enable_reg = 0x3734,
2308 .enable_mask = BIT(0),
2320 .halt_reg = 0x3738,
2322 .enable_reg = 0x3738,
2323 .enable_mask = BIT(0),
2335 .halt_reg = 0x373c,
2337 .enable_reg = 0x373c,
2338 .enable_mask = BIT(0),
2350 .halt_reg = 0x3740,
2352 .enable_reg = 0x3740,
2353 .enable_mask = BIT(0),
2365 .halt_reg = 0x3744,
2367 .enable_reg = 0x3744,
2368 .enable_mask = BIT(0),
2380 .halt_reg = 0x3748,
2382 .enable_reg = 0x3748,
2383 .enable_mask = BIT(0),
2395 .halt_reg = 0x3b68,
2397 .enable_reg = 0x3b68,
2398 .enable_mask = BIT(0),
2410 .halt_reg = 0x3b6c,
2412 .enable_reg = 0x3b6c,
2413 .enable_mask = BIT(0),
2425 .halt_reg = 0x3b74,
2427 .enable_reg = 0x3b74,
2428 .enable_mask = BIT(0),
2440 .halt_reg = 0x5024,
2443 .enable_reg = 0x5024,
2444 .enable_mask = BIT(0),
2456 .halt_reg = 0xe004,
2458 .hwcg_reg = 0xe004,
2461 .enable_reg = 0xe004,
2462 .enable_mask = BIT(0),
2474 .halt_reg = 0xe008,
2476 .hwcg_reg = 0xe008,
2479 .enable_reg = 0xe008,
2480 .enable_mask = BIT(0),
2491 .halt_reg = 0xf004,
2493 .enable_reg = 0xf004,
2494 .enable_mask = BIT(0),
2506 .halt_reg = 0xf064,
2508 .enable_reg = 0xf064,
2509 .enable_mask = BIT(0),
2521 .halt_reg = 0xf068,
2523 .enable_reg = 0xf068,
2524 .enable_mask = BIT(0),
2536 .gdscr = 0x1024,
2537 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2546 .gdscr = 0x1040,
2547 .cxcs = (unsigned int []){ 0x1048 },
2558 .gdscr = 0x1044,
2559 .cxcs = (unsigned int []){ 0x104c },
2570 .gdscr = 0x2304,
2571 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2580 .gdscr = 0x34a0,
2581 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2582 0x35a8, 0x3868 },
2591 .gdscr = 0x3664,
2600 .gdscr = 0x3674,
2609 .gdscr = 0x36d4,
2618 .gdscr = 0xe020,
2619 .gds_hw_ctrl = 0xe024,
2620 .cxcs = (unsigned int []){ 0xe008 },
2791 [SPDM_BCR] = { 0x200 },
2792 [SPDM_RM_BCR] = { 0x300 },
2793 [MISC_BCR] = { 0x320 },
2794 [VIDEO_TOP_BCR] = { 0x1020 },
2795 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2796 [MDSS_BCR] = { 0x2300 },
2797 [THROTTLE_MDSS_BCR] = { 0x2460 },
2798 [CAMSS_PHY0_BCR] = { 0x3020 },
2799 [CAMSS_PHY1_BCR] = { 0x3050 },
2800 [CAMSS_PHY2_BCR] = { 0x3080 },
2801 [CAMSS_CSI0_BCR] = { 0x30b0 },
2802 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2803 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2804 [CAMSS_CSI1_BCR] = { 0x3120 },
2805 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2806 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2807 [CAMSS_CSI2_BCR] = { 0x3180 },
2808 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2809 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2810 [CAMSS_CSI3_BCR] = { 0x31e0 },
2811 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2812 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2813 [CAMSS_ISPIF_BCR] = { 0x3220 },
2814 [CAMSS_CCI_BCR] = { 0x3340 },
2815 [CAMSS_TOP_BCR] = { 0x3480 },
2816 [CAMSS_AHB_BCR] = { 0x3488 },
2817 [CAMSS_MICRO_BCR] = { 0x3490 },
2818 [CAMSS_JPEG_BCR] = { 0x35a0 },
2819 [CAMSS_VFE0_BCR] = { 0x3660 },
2820 [CAMSS_VFE1_BCR] = { 0x3670 },
2821 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2822 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2823 [CAMSS_CPP_BCR] = { 0x36d0 },
2824 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2825 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2826 [CAMSS_FD_BCR] = { 0x3b60 },
2827 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2828 [MNOCAHB_BCR] = { 0x5020 },
2829 [MNOCAXI_BCR] = { 0xd020 },
2830 [BMIC_SMMU_BCR] = { 0xe000 },
2831 [MNOC_MAXI_BCR] = { 0xf000 },
2832 [VMEM_BCR] = { 0xf060 },
2833 [BTO_BCR] = { 0x10004 },
2840 .max_register = 0x10004,