Lines Matching +full:0 +full:x3b00
44 { P_XO, 0 },
54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
91 { 1500000000, 2000000000, 0 },
95 { 500000000, 1500000000, 0 },
99 .post_div_mask = 0xf00,
103 .offset = 0x0,
108 .enable_reg = 0x100,
109 .enable_mask = BIT(0),
122 .offset = 0x0,
135 .offset = 0x30,
140 .enable_reg = 0x100,
154 .offset = 0x30,
167 .offset = 0x60,
182 .offset = 0x60,
195 .offset = 0x90,
210 .offset = 0x90,
223 { P_XO, 0 },
235 { P_XO, 0 },
247 { P_XO, 0 },
261 { P_XO, 0 },
275 .offset = 0xc0,
290 .offset = 0xc0,
304 F(19200000, P_XO, 1, 0, 0),
305 F(40000000, P_GPLL0, 15, 0, 0),
306 F(80000000, P_MMPLL0, 10, 0, 0),
311 .cmd_rcgr = 0x5000,
324 F(75000000, P_GPLL0, 8, 0, 0),
325 F(150000000, P_GPLL0, 4, 0, 0),
326 F(333430000, P_MMPLL1, 3.5, 0, 0),
327 F(466800000, P_MMPLL1, 2.5, 0, 0),
332 F(75000000, P_GPLL0, 8, 0, 0),
333 F(150000000, P_GPLL0, 4, 0, 0),
334 F(300000000, P_GPLL0, 2, 0, 0),
335 F(404000000, P_MMPLL1, 2, 0, 0),
340 .cmd_rcgr = 0x5040,
353 F(100000000, P_GPLL0, 6, 0, 0),
354 F(240000000, P_GPLL0, 2.5, 0, 0),
355 F(266670000, P_MMPLL0, 3, 0, 0),
360 F(100000000, P_GPLL0, 6, 0, 0),
361 F(266670000, P_MMPLL0, 3, 0, 0),
366 .cmd_rcgr = 0x3090,
379 F(66670000, P_GPLL0, 9, 0, 0),
380 F(100000000, P_GPLL0, 6, 0, 0),
381 F(133330000, P_GPLL0, 4.5, 0, 0),
382 F(150000000, P_GPLL0, 4, 0, 0),
383 F(200000000, P_MMPLL0, 4, 0, 0),
384 F(240000000, P_GPLL0, 2.5, 0, 0),
385 F(266670000, P_MMPLL0, 3, 0, 0),
386 F(320000000, P_MMPLL0, 2.5, 0, 0),
387 F(510000000, P_MMPLL3, 2, 0, 0),
392 F(66670000, P_GPLL0, 9, 0, 0),
393 F(100000000, P_GPLL0, 6, 0, 0),
394 F(133330000, P_GPLL0, 4.5, 0, 0),
395 F(200000000, P_MMPLL0, 4, 0, 0),
396 F(320000000, P_MMPLL0, 2.5, 0, 0),
397 F(510000000, P_MMPLL3, 2, 0, 0),
402 .cmd_rcgr = 0x1000,
416 .cmd_rcgr = 0x3100,
429 .cmd_rcgr = 0x3160,
442 .cmd_rcgr = 0x31c0,
455 F(80000000, P_GPLL0, 7.5, 0, 0),
456 F(100000000, P_GPLL0, 6, 0, 0),
457 F(200000000, P_GPLL0, 3, 0, 0),
458 F(320000000, P_MMPLL0, 2.5, 0, 0),
459 F(400000000, P_MMPLL0, 2, 0, 0),
460 F(480000000, P_MMPLL4, 2, 0, 0),
461 F(533330000, P_MMPLL0, 1.5, 0, 0),
462 F(600000000, P_GPLL0, 1, 0, 0),
467 F(80000000, P_GPLL0, 7.5, 0, 0),
468 F(100000000, P_GPLL0, 6, 0, 0),
469 F(200000000, P_GPLL0, 3, 0, 0),
470 F(320000000, P_MMPLL0, 2.5, 0, 0),
471 F(480000000, P_MMPLL4, 2, 0, 0),
472 F(600000000, P_GPLL0, 1, 0, 0),
477 .cmd_rcgr = 0x3600,
490 F(80000000, P_GPLL0, 7.5, 0, 0),
491 F(100000000, P_GPLL0, 6, 0, 0),
492 F(200000000, P_GPLL0, 3, 0, 0),
493 F(320000000, P_MMPLL0, 2.5, 0, 0),
494 F(400000000, P_MMPLL0, 2, 0, 0),
495 F(533330000, P_MMPLL0, 1.5, 0, 0),
500 .cmd_rcgr = 0x3620,
513 F(100000000, P_GPLL0, 6, 0, 0),
514 F(200000000, P_GPLL0, 3, 0, 0),
515 F(320000000, P_MMPLL0, 2.5, 0, 0),
516 F(480000000, P_MMPLL4, 2, 0, 0),
517 F(600000000, P_GPLL0, 1, 0, 0),
518 F(640000000, P_MMPLL4, 1.5, 0, 0),
523 F(100000000, P_GPLL0, 6, 0, 0),
524 F(200000000, P_GPLL0, 3, 0, 0),
525 F(320000000, P_MMPLL0, 2.5, 0, 0),
526 F(480000000, P_MMPLL4, 2, 0, 0),
527 F(640000000, P_MMPLL4, 1.5, 0, 0),
532 .cmd_rcgr = 0x3640,
545 F(75000000, P_GPLL0, 8, 0, 0),
546 F(150000000, P_GPLL0, 4, 0, 0),
547 F(228570000, P_MMPLL0, 3.5, 0, 0),
548 F(266670000, P_MMPLL0, 3, 0, 0),
549 F(320000000, P_MMPLL0, 2.5, 0, 0),
550 F(480000000, P_MMPLL4, 2, 0, 0),
555 .cmd_rcgr = 0x3520,
568 F(75000000, P_GPLL0, 8, 0, 0),
569 F(133330000, P_GPLL0, 4.5, 0, 0),
570 F(150000000, P_GPLL0, 4, 0, 0),
571 F(228570000, P_MMPLL0, 3.5, 0, 0),
572 F(266670000, P_MMPLL0, 3, 0, 0),
573 F(320000000, P_MMPLL0, 2.5, 0, 0),
578 .cmd_rcgr = 0x3540,
591 F(50000000, P_GPLL0, 12, 0, 0),
592 F(100000000, P_GPLL0, 6, 0, 0),
593 F(200000000, P_MMPLL0, 4, 0, 0),
598 .cmd_rcgr = 0x3060,
611 F(60000000, P_GPLL0, 10, 0, 0),
612 F(200000000, P_GPLL0, 3, 0, 0),
613 F(320000000, P_MMPLL0, 2.5, 0, 0),
614 F(400000000, P_MMPLL0, 2, 0, 0),
619 .cmd_rcgr = 0x3b00,
632 F(85710000, P_GPLL0, 7, 0, 0),
633 F(100000000, P_GPLL0, 6, 0, 0),
634 F(120000000, P_GPLL0, 5, 0, 0),
635 F(150000000, P_GPLL0, 4, 0, 0),
636 F(171430000, P_GPLL0, 3.5, 0, 0),
637 F(200000000, P_GPLL0, 3, 0, 0),
638 F(240000000, P_GPLL0, 2.5, 0, 0),
639 F(266670000, P_MMPLL0, 3, 0, 0),
640 F(300000000, P_GPLL0, 2, 0, 0),
641 F(320000000, P_MMPLL0, 2.5, 0, 0),
642 F(400000000, P_MMPLL0, 2, 0, 0),
647 F(85710000, P_GPLL0, 7, 0, 0),
648 F(171430000, P_GPLL0, 3.5, 0, 0),
649 F(200000000, P_GPLL0, 3, 0, 0),
650 F(240000000, P_GPLL0, 2.5, 0, 0),
651 F(266670000, P_MMPLL0, 3, 0, 0),
652 F(320000000, P_MMPLL0, 2.5, 0, 0),
653 F(400000000, P_MMPLL0, 2, 0, 0),
658 .cmd_rcgr = 0x2040,
671 .cmd_rcgr = 0x2000,
685 .cmd_rcgr = 0x2020,
699 F(19200000, P_XO, 1, 0, 0),
700 F(75000000, P_GPLL0, 8, 0, 0),
701 F(100000000, P_GPLL0, 6, 0, 0),
702 F(150000000, P_GPLL0, 4, 0, 0),
703 F(228570000, P_MMPLL0, 3.5, 0, 0),
704 F(266670000, P_MMPLL0, 3, 0, 0),
705 F(320000000, P_MMPLL0, 2.5, 0, 0),
706 F(400000000, P_MMPLL0, 2, 0, 0),
711 F(19200000, P_XO, 1, 0, 0),
712 F(75000000, P_GPLL0, 8, 0, 0),
713 F(100000000, P_GPLL0, 6, 0, 0),
714 F(150000000, P_GPLL0, 4, 0, 0),
715 F(320000000, P_MMPLL0, 2.5, 0, 0),
716 F(400000000, P_MMPLL0, 2, 0, 0),
721 .cmd_rcgr = 0x5090,
734 F(19200000, P_XO, 1, 0, 0),
735 F(37500000, P_GPLL0, 16, 0, 0),
736 F(50000000, P_GPLL0, 12, 0, 0),
737 F(100000000, P_GPLL0, 6, 0, 0),
742 .cmd_rcgr = 0x3300,
766 .cmd_rcgr = 0x3420,
780 .cmd_rcgr = 0x3450,
794 .cmd_rcgr = 0x3500,
807 .cmd_rcgr = 0x3560,
820 F(4800000, P_XO, 4, 0, 0),
823 F(9600000, P_XO, 2, 0, 0),
825 F(19200000, P_XO, 1, 0, 0),
828 F(48000000, P_GPLL0, 12.5, 0, 0),
829 F(64000000, P_MMPLL0, 12.5, 0, 0),
834 F(4800000, P_XO, 4, 0, 0),
837 F(9600000, P_XO, 2, 0, 0),
840 F(19200000, P_XO, 1, 0, 0),
844 F(64000000, P_MMPLL4, 15, 0, 0),
849 F(4800000, P_XO, 4, 0, 0),
852 F(9600000, P_XO, 2, 0, 0),
854 F(19200000, P_XO, 1, 0, 0),
858 F(64000000, P_MMPLL4, 15, 0, 0),
863 .cmd_rcgr = 0x3360,
877 .cmd_rcgr = 0x3390,
891 .cmd_rcgr = 0x33c0,
905 .cmd_rcgr = 0x33f0,
919 F(50000000, P_GPLL0, 12, 0, 0),
920 F(100000000, P_GPLL0, 6, 0, 0),
921 F(200000000, P_MMPLL0, 4, 0, 0),
926 .cmd_rcgr = 0x3000,
939 .cmd_rcgr = 0x3030,
952 .cmd_rcgr = 0x2120,
965 .cmd_rcgr = 0x2140,
978 F(19200000, P_XO, 1, 0, 0),
983 .cmd_rcgr = 0x2160,
996 .cmd_rcgr = 0x2180,
1014 .cmd_rcgr = 0x2060,
1028 F(19200000, P_XO, 1, 0, 0),
1033 .cmd_rcgr = 0x2100,
1046 F(19200000, P_XO, 1, 0, 0),
1051 .cmd_rcgr = 0x2080,
1064 F(19200000, P_XO, 1, 0, 0),
1069 .cmd_rcgr = 0x4090,
1082 .halt_reg = 0x348c,
1084 .enable_reg = 0x348c,
1085 .enable_mask = BIT(0),
1097 .halt_reg = 0x3348,
1099 .enable_reg = 0x3348,
1100 .enable_mask = BIT(0),
1112 .halt_reg = 0x3344,
1114 .enable_reg = 0x3344,
1115 .enable_mask = BIT(0),
1126 .halt_reg = 0x36b4,
1128 .enable_reg = 0x36b4,
1129 .enable_mask = BIT(0),
1141 .halt_reg = 0x36c4,
1143 .enable_reg = 0x36c4,
1144 .enable_mask = BIT(0),
1155 .halt_reg = 0x36b0,
1157 .enable_reg = 0x36b0,
1158 .enable_mask = BIT(0),
1169 .halt_reg = 0x30bc,
1171 .enable_reg = 0x30bc,
1172 .enable_mask = BIT(0),
1184 .halt_reg = 0x30b4,
1186 .enable_reg = 0x30b4,
1187 .enable_mask = BIT(0),
1198 .halt_reg = 0x30c4,
1200 .enable_reg = 0x30c4,
1201 .enable_mask = BIT(0),
1212 .halt_reg = 0x30e4,
1214 .enable_reg = 0x30e4,
1215 .enable_mask = BIT(0),
1226 .halt_reg = 0x30d4,
1228 .enable_reg = 0x30d4,
1229 .enable_mask = BIT(0),
1240 .halt_reg = 0x3128,
1242 .enable_reg = 0x3128,
1243 .enable_mask = BIT(0),
1255 .halt_reg = 0x3124,
1257 .enable_reg = 0x3124,
1258 .enable_mask = BIT(0),
1269 .halt_reg = 0x3134,
1271 .enable_reg = 0x3134,
1272 .enable_mask = BIT(0),
1283 .halt_reg = 0x3154,
1285 .enable_reg = 0x3154,
1286 .enable_mask = BIT(0),
1297 .halt_reg = 0x3144,
1299 .enable_reg = 0x3144,
1300 .enable_mask = BIT(0),
1311 .halt_reg = 0x3188,
1313 .enable_reg = 0x3188,
1314 .enable_mask = BIT(0),
1326 .halt_reg = 0x3184,
1328 .enable_reg = 0x3184,
1329 .enable_mask = BIT(0),
1340 .halt_reg = 0x3194,
1342 .enable_reg = 0x3194,
1343 .enable_mask = BIT(0),
1354 .halt_reg = 0x31b4,
1356 .enable_reg = 0x31b4,
1357 .enable_mask = BIT(0),
1368 .halt_reg = 0x31a4,
1370 .enable_reg = 0x31a4,
1371 .enable_mask = BIT(0),
1382 .halt_reg = 0x31e8,
1384 .enable_reg = 0x31e8,
1385 .enable_mask = BIT(0),
1397 .halt_reg = 0x31e4,
1399 .enable_reg = 0x31e4,
1400 .enable_mask = BIT(0),
1411 .halt_reg = 0x31f4,
1413 .enable_reg = 0x31f4,
1414 .enable_mask = BIT(0),
1425 .halt_reg = 0x3214,
1427 .enable_reg = 0x3214,
1428 .enable_mask = BIT(0),
1439 .halt_reg = 0x3204,
1441 .enable_reg = 0x3204,
1442 .enable_mask = BIT(0),
1453 .halt_reg = 0x3704,
1455 .enable_reg = 0x3704,
1456 .enable_mask = BIT(0),
1467 .halt_reg = 0x3714,
1469 .enable_reg = 0x3714,
1470 .enable_mask = BIT(0),
1481 .halt_reg = 0x3444,
1483 .enable_reg = 0x3444,
1484 .enable_mask = BIT(0),
1495 .halt_reg = 0x3474,
1497 .enable_reg = 0x3474,
1498 .enable_mask = BIT(0),
1509 .halt_reg = 0x3224,
1511 .enable_reg = 0x3224,
1512 .enable_mask = BIT(0),
1524 .halt_reg = 0x35c0,
1526 .enable_reg = 0x35c0,
1527 .enable_mask = BIT(0),
1538 .halt_reg = 0x35a8,
1540 .enable_reg = 0x35a8,
1541 .enable_mask = BIT(0),
1552 .halt_reg = 0x35ac,
1554 .enable_reg = 0x35ac,
1555 .enable_mask = BIT(0),
1566 .halt_reg = 0x35b0,
1568 .enable_reg = 0x35b0,
1569 .enable_mask = BIT(0),
1580 .halt_reg = 0x35b4,
1582 .enable_reg = 0x35b4,
1583 .enable_mask = BIT(0),
1595 .halt_reg = 0x35b8,
1597 .enable_reg = 0x35b8,
1598 .enable_mask = BIT(0),
1609 .halt_reg = 0x3384,
1611 .enable_reg = 0x3384,
1612 .enable_mask = BIT(0),
1623 .halt_reg = 0x33b4,
1625 .enable_reg = 0x33b4,
1626 .enable_mask = BIT(0),
1637 .halt_reg = 0x33e4,
1639 .enable_reg = 0x33e4,
1640 .enable_mask = BIT(0),
1651 .halt_reg = 0x3414,
1653 .enable_reg = 0x3414,
1654 .enable_mask = BIT(0),
1665 .halt_reg = 0x3494,
1667 .enable_reg = 0x3494,
1668 .enable_mask = BIT(0),
1680 .halt_reg = 0x3024,
1682 .enable_reg = 0x3024,
1683 .enable_mask = BIT(0),
1694 .halt_reg = 0x3054,
1696 .enable_reg = 0x3054,
1697 .enable_mask = BIT(0),
1708 .halt_reg = 0x3084,
1710 .enable_reg = 0x3084,
1711 .enable_mask = BIT(0),
1722 .halt_reg = 0x3484,
1724 .enable_reg = 0x3484,
1725 .enable_mask = BIT(0),
1737 .halt_reg = 0x36a8,
1739 .enable_reg = 0x36a8,
1740 .enable_mask = BIT(0),
1751 .halt_reg = 0x36ac,
1753 .enable_reg = 0x36ac,
1754 .enable_mask = BIT(0),
1765 .halt_reg = 0x36b8,
1767 .enable_reg = 0x36b8,
1768 .enable_mask = BIT(0),
1780 .halt_reg = 0x36bc,
1782 .enable_reg = 0x36bc,
1783 .enable_mask = BIT(0),
1794 .halt_reg = 0x3b74,
1796 .enable_reg = 0x3b74,
1797 .enable_mask = BIT(0),
1808 .halt_reg = 0x3b70,
1810 .enable_reg = 0x3b70,
1811 .enable_mask = BIT(0),
1822 .halt_reg = 0x3b68,
1824 .enable_reg = 0x3b68,
1825 .enable_mask = BIT(0),
1836 .halt_reg = 0x3b6c,
1838 .enable_reg = 0x3b6c,
1839 .enable_mask = BIT(0),
1850 .halt_reg = 0x2308,
1853 .enable_reg = 0x2308,
1854 .enable_mask = BIT(0),
1866 .halt_reg = 0x2310,
1868 .enable_reg = 0x2310,
1869 .enable_mask = BIT(0),
1881 .halt_reg = 0x233c,
1883 .enable_reg = 0x233c,
1884 .enable_mask = BIT(0),
1896 .halt_reg = 0x2340,
1898 .enable_reg = 0x2340,
1899 .enable_mask = BIT(0),
1911 .halt_reg = 0x2344,
1913 .enable_reg = 0x2344,
1914 .enable_mask = BIT(0),
1926 .halt_reg = 0x2348,
1928 .enable_reg = 0x2348,
1929 .enable_mask = BIT(0),
1941 .halt_reg = 0x2324,
1943 .enable_reg = 0x2324,
1944 .enable_mask = BIT(0),
1956 .halt_reg = 0x230c,
1958 .enable_reg = 0x230c,
1959 .enable_mask = BIT(0),
1971 .halt_reg = 0x2338,
1973 .enable_reg = 0x2338,
1974 .enable_mask = BIT(0),
1986 .halt_reg = 0x231c,
1988 .enable_reg = 0x231c,
1989 .enable_mask = BIT(0),
2001 .halt_reg = 0x2314,
2003 .enable_reg = 0x2314,
2004 .enable_mask = BIT(0),
2016 .halt_reg = 0x2318,
2018 .enable_reg = 0x2318,
2019 .enable_mask = BIT(0),
2031 .halt_reg = 0x2328,
2033 .enable_reg = 0x2328,
2034 .enable_mask = BIT(0),
2046 .halt_reg = 0x502c,
2048 .enable_reg = 0x502c,
2049 .enable_mask = BIT(0),
2061 .halt_reg = 0x506c,
2063 .enable_reg = 0x506c,
2064 .enable_mask = BIT(0),
2077 .halt_reg = 0x5064,
2079 .enable_reg = 0x5064,
2080 .enable_mask = BIT(0),
2092 .halt_reg = 0x4058,
2094 .enable_reg = 0x4058,
2095 .enable_mask = BIT(0),
2107 .halt_reg = 0x4028,
2109 .enable_reg = 0x4028,
2110 .enable_mask = BIT(0),
2125 .halt_reg = 0x40b0,
2127 .enable_reg = 0x40b0,
2128 .enable_mask = BIT(0),
2140 .halt_reg = 0x403c,
2142 .enable_reg = 0x403c,
2143 .enable_mask = BIT(0),
2155 .halt_reg = 0x1030,
2157 .enable_reg = 0x1030,
2158 .enable_mask = BIT(0),
2170 .halt_reg = 0x1034,
2172 .enable_reg = 0x1034,
2173 .enable_mask = BIT(0),
2184 .halt_reg = 0x1038,
2186 .enable_reg = 0x1038,
2187 .enable_mask = BIT(0),
2199 .halt_reg = 0x1028,
2201 .enable_reg = 0x1028,
2202 .enable_mask = BIT(0),
2214 .halt_reg = 0x1048,
2216 .enable_reg = 0x1048,
2217 .enable_mask = BIT(0),
2229 .halt_reg = 0x104c,
2231 .enable_reg = 0x104c,
2232 .enable_mask = BIT(0),
2244 .halt_reg = 0x1054,
2246 .enable_reg = 0x1054,
2247 .enable_mask = BIT(0),
2259 .gdscr = 0x1024,
2260 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2269 .gdscr = 0x1040,
2270 .cxcs = (unsigned int []){ 0x1048 },
2280 .gdscr = 0x1044,
2281 .cxcs = (unsigned int []){ 0x104c },
2291 .gdscr = 0x1050,
2292 .cxcs = (unsigned int []){ 0x1054 },
2302 .gdscr = 0x2304,
2303 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2312 .gdscr = 0x34a0,
2313 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2322 .gdscr = 0x35a4,
2323 .cxcs = (unsigned int []){ 0x35a8 },
2333 .gdscr = 0x36a4,
2334 .cxcs = (unsigned int []){ 0x36bc },
2344 .gdscr = 0x36d4,
2345 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2355 .gdscr = 0x3b64,
2356 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2364 .gdscr = 0x4034,
2373 .gdscr = 0x4024,
2374 .cxcs = (unsigned int []){ 0x4028 },
2531 [CAMSS_MICRO_BCR] = { 0x3490 },
2538 .max_register = 0x5200,