Lines Matching +full:0 +full:x104c
43 { P_XO, 0 },
53 { P_XO, 0 },
63 { P_XO, 0 },
75 { P_XO, 0 },
90 { 1500000000, 2000000000, 0 },
94 { 500000000, 1500000000, 0 },
98 .post_div_mask = 0xf00,
102 .offset = 0x0,
107 .enable_reg = 0x100,
108 .enable_mask = BIT(0),
121 .offset = 0x0,
134 .offset = 0x30,
139 .enable_reg = 0x100,
153 .offset = 0x30,
166 .offset = 0x60,
181 .offset = 0x60,
194 .offset = 0x90,
209 .offset = 0x90,
222 { P_XO, 0 },
234 { P_XO, 0 },
246 { P_XO, 0 },
260 { P_XO, 0 },
274 .offset = 0xc0,
289 .offset = 0xc0,
303 F(19200000, P_XO, 1, 0, 0),
304 F(40000000, P_GPLL0, 15, 0, 0),
305 F(80000000, P_MMPLL0, 10, 0, 0),
310 .cmd_rcgr = 0x5000,
323 F(75000000, P_GPLL0, 8, 0, 0),
324 F(150000000, P_GPLL0, 4, 0, 0),
325 F(333430000, P_MMPLL1, 3.5, 0, 0),
326 F(466800000, P_MMPLL1, 2.5, 0, 0),
331 F(75000000, P_GPLL0, 8, 0, 0),
332 F(150000000, P_GPLL0, 4, 0, 0),
333 F(300000000, P_GPLL0, 2, 0, 0),
334 F(404000000, P_MMPLL1, 2, 0, 0),
339 .cmd_rcgr = 0x5040,
352 F(100000000, P_GPLL0, 6, 0, 0),
353 F(240000000, P_GPLL0, 2.5, 0, 0),
354 F(266670000, P_MMPLL0, 3, 0, 0),
359 F(100000000, P_GPLL0, 6, 0, 0),
360 F(266670000, P_MMPLL0, 3, 0, 0),
365 .cmd_rcgr = 0x3090,
378 F(66670000, P_GPLL0, 9, 0, 0),
379 F(100000000, P_GPLL0, 6, 0, 0),
380 F(133330000, P_GPLL0, 4.5, 0, 0),
381 F(150000000, P_GPLL0, 4, 0, 0),
382 F(200000000, P_MMPLL0, 4, 0, 0),
383 F(240000000, P_GPLL0, 2.5, 0, 0),
384 F(266670000, P_MMPLL0, 3, 0, 0),
385 F(320000000, P_MMPLL0, 2.5, 0, 0),
386 F(510000000, P_MMPLL3, 2, 0, 0),
391 F(66670000, P_GPLL0, 9, 0, 0),
392 F(100000000, P_GPLL0, 6, 0, 0),
393 F(133330000, P_GPLL0, 4.5, 0, 0),
394 F(200000000, P_MMPLL0, 4, 0, 0),
395 F(320000000, P_MMPLL0, 2.5, 0, 0),
396 F(510000000, P_MMPLL3, 2, 0, 0),
401 .cmd_rcgr = 0x1000,
415 .cmd_rcgr = 0x3100,
428 .cmd_rcgr = 0x3160,
441 .cmd_rcgr = 0x31c0,
454 F(80000000, P_GPLL0, 7.5, 0, 0),
455 F(100000000, P_GPLL0, 6, 0, 0),
456 F(200000000, P_GPLL0, 3, 0, 0),
457 F(320000000, P_MMPLL0, 2.5, 0, 0),
458 F(400000000, P_MMPLL0, 2, 0, 0),
459 F(480000000, P_MMPLL4, 2, 0, 0),
460 F(533330000, P_MMPLL0, 1.5, 0, 0),
461 F(600000000, P_GPLL0, 1, 0, 0),
466 F(80000000, P_GPLL0, 7.5, 0, 0),
467 F(100000000, P_GPLL0, 6, 0, 0),
468 F(200000000, P_GPLL0, 3, 0, 0),
469 F(320000000, P_MMPLL0, 2.5, 0, 0),
470 F(480000000, P_MMPLL4, 2, 0, 0),
471 F(600000000, P_GPLL0, 1, 0, 0),
476 .cmd_rcgr = 0x3600,
489 F(80000000, P_GPLL0, 7.5, 0, 0),
490 F(100000000, P_GPLL0, 6, 0, 0),
491 F(200000000, P_GPLL0, 3, 0, 0),
492 F(320000000, P_MMPLL0, 2.5, 0, 0),
493 F(400000000, P_MMPLL0, 2, 0, 0),
494 F(533330000, P_MMPLL0, 1.5, 0, 0),
499 .cmd_rcgr = 0x3620,
512 F(100000000, P_GPLL0, 6, 0, 0),
513 F(200000000, P_GPLL0, 3, 0, 0),
514 F(320000000, P_MMPLL0, 2.5, 0, 0),
515 F(480000000, P_MMPLL4, 2, 0, 0),
516 F(600000000, P_GPLL0, 1, 0, 0),
517 F(640000000, P_MMPLL4, 1.5, 0, 0),
522 F(100000000, P_GPLL0, 6, 0, 0),
523 F(200000000, P_GPLL0, 3, 0, 0),
524 F(320000000, P_MMPLL0, 2.5, 0, 0),
525 F(480000000, P_MMPLL4, 2, 0, 0),
526 F(640000000, P_MMPLL4, 1.5, 0, 0),
531 .cmd_rcgr = 0x3640,
544 F(75000000, P_GPLL0, 8, 0, 0),
545 F(150000000, P_GPLL0, 4, 0, 0),
546 F(228570000, P_MMPLL0, 3.5, 0, 0),
547 F(266670000, P_MMPLL0, 3, 0, 0),
548 F(320000000, P_MMPLL0, 2.5, 0, 0),
549 F(480000000, P_MMPLL4, 2, 0, 0),
554 .cmd_rcgr = 0x3520,
567 F(75000000, P_GPLL0, 8, 0, 0),
568 F(133330000, P_GPLL0, 4.5, 0, 0),
569 F(150000000, P_GPLL0, 4, 0, 0),
570 F(228570000, P_MMPLL0, 3.5, 0, 0),
571 F(266670000, P_MMPLL0, 3, 0, 0),
572 F(320000000, P_MMPLL0, 2.5, 0, 0),
577 .cmd_rcgr = 0x3540,
590 F(50000000, P_GPLL0, 12, 0, 0),
591 F(100000000, P_GPLL0, 6, 0, 0),
592 F(200000000, P_MMPLL0, 4, 0, 0),
597 .cmd_rcgr = 0x3060,
610 F(60000000, P_GPLL0, 10, 0, 0),
611 F(200000000, P_GPLL0, 3, 0, 0),
612 F(320000000, P_MMPLL0, 2.5, 0, 0),
613 F(400000000, P_MMPLL0, 2, 0, 0),
618 .cmd_rcgr = 0x3b00,
631 F(85710000, P_GPLL0, 7, 0, 0),
632 F(100000000, P_GPLL0, 6, 0, 0),
633 F(120000000, P_GPLL0, 5, 0, 0),
634 F(150000000, P_GPLL0, 4, 0, 0),
635 F(171430000, P_GPLL0, 3.5, 0, 0),
636 F(200000000, P_GPLL0, 3, 0, 0),
637 F(240000000, P_GPLL0, 2.5, 0, 0),
638 F(266670000, P_MMPLL0, 3, 0, 0),
639 F(300000000, P_GPLL0, 2, 0, 0),
640 F(320000000, P_MMPLL0, 2.5, 0, 0),
641 F(400000000, P_MMPLL0, 2, 0, 0),
646 F(85710000, P_GPLL0, 7, 0, 0),
647 F(171430000, P_GPLL0, 3.5, 0, 0),
648 F(200000000, P_GPLL0, 3, 0, 0),
649 F(240000000, P_GPLL0, 2.5, 0, 0),
650 F(266670000, P_MMPLL0, 3, 0, 0),
651 F(320000000, P_MMPLL0, 2.5, 0, 0),
652 F(400000000, P_MMPLL0, 2, 0, 0),
657 .cmd_rcgr = 0x2040,
670 .cmd_rcgr = 0x2000,
684 .cmd_rcgr = 0x2020,
698 F(19200000, P_XO, 1, 0, 0),
699 F(75000000, P_GPLL0, 8, 0, 0),
700 F(100000000, P_GPLL0, 6, 0, 0),
701 F(150000000, P_GPLL0, 4, 0, 0),
702 F(228570000, P_MMPLL0, 3.5, 0, 0),
703 F(266670000, P_MMPLL0, 3, 0, 0),
704 F(320000000, P_MMPLL0, 2.5, 0, 0),
705 F(400000000, P_MMPLL0, 2, 0, 0),
710 F(19200000, P_XO, 1, 0, 0),
711 F(75000000, P_GPLL0, 8, 0, 0),
712 F(100000000, P_GPLL0, 6, 0, 0),
713 F(150000000, P_GPLL0, 4, 0, 0),
714 F(320000000, P_MMPLL0, 2.5, 0, 0),
715 F(400000000, P_MMPLL0, 2, 0, 0),
720 .cmd_rcgr = 0x5090,
733 F(19200000, P_XO, 1, 0, 0),
734 F(37500000, P_GPLL0, 16, 0, 0),
735 F(50000000, P_GPLL0, 12, 0, 0),
736 F(100000000, P_GPLL0, 6, 0, 0),
741 .cmd_rcgr = 0x3300,
765 .cmd_rcgr = 0x3420,
779 .cmd_rcgr = 0x3450,
793 .cmd_rcgr = 0x3500,
806 .cmd_rcgr = 0x3560,
819 F(4800000, P_XO, 4, 0, 0),
822 F(9600000, P_XO, 2, 0, 0),
824 F(19200000, P_XO, 1, 0, 0),
827 F(48000000, P_GPLL0, 12.5, 0, 0),
828 F(64000000, P_MMPLL0, 12.5, 0, 0),
833 F(4800000, P_XO, 4, 0, 0),
836 F(9600000, P_XO, 2, 0, 0),
839 F(19200000, P_XO, 1, 0, 0),
843 F(64000000, P_MMPLL4, 15, 0, 0),
848 F(4800000, P_XO, 4, 0, 0),
851 F(9600000, P_XO, 2, 0, 0),
853 F(19200000, P_XO, 1, 0, 0),
857 F(64000000, P_MMPLL4, 15, 0, 0),
862 .cmd_rcgr = 0x3360,
876 .cmd_rcgr = 0x3390,
890 .cmd_rcgr = 0x33c0,
904 .cmd_rcgr = 0x33f0,
918 F(50000000, P_GPLL0, 12, 0, 0),
919 F(100000000, P_GPLL0, 6, 0, 0),
920 F(200000000, P_MMPLL0, 4, 0, 0),
925 .cmd_rcgr = 0x3000,
938 .cmd_rcgr = 0x3030,
951 .cmd_rcgr = 0x2120,
964 .cmd_rcgr = 0x2140,
977 F(19200000, P_XO, 1, 0, 0),
982 .cmd_rcgr = 0x2160,
995 .cmd_rcgr = 0x2180,
1013 .cmd_rcgr = 0x2060,
1027 F(19200000, P_XO, 1, 0, 0),
1032 .cmd_rcgr = 0x2100,
1045 F(19200000, P_XO, 1, 0, 0),
1050 .cmd_rcgr = 0x2080,
1063 F(19200000, P_XO, 1, 0, 0),
1068 .cmd_rcgr = 0x4090,
1081 .halt_reg = 0x348c,
1083 .enable_reg = 0x348c,
1084 .enable_mask = BIT(0),
1096 .halt_reg = 0x3348,
1098 .enable_reg = 0x3348,
1099 .enable_mask = BIT(0),
1111 .halt_reg = 0x3344,
1113 .enable_reg = 0x3344,
1114 .enable_mask = BIT(0),
1125 .halt_reg = 0x36b4,
1127 .enable_reg = 0x36b4,
1128 .enable_mask = BIT(0),
1140 .halt_reg = 0x36c4,
1142 .enable_reg = 0x36c4,
1143 .enable_mask = BIT(0),
1154 .halt_reg = 0x36b0,
1156 .enable_reg = 0x36b0,
1157 .enable_mask = BIT(0),
1168 .halt_reg = 0x30bc,
1170 .enable_reg = 0x30bc,
1171 .enable_mask = BIT(0),
1183 .halt_reg = 0x30b4,
1185 .enable_reg = 0x30b4,
1186 .enable_mask = BIT(0),
1197 .halt_reg = 0x30c4,
1199 .enable_reg = 0x30c4,
1200 .enable_mask = BIT(0),
1211 .halt_reg = 0x30e4,
1213 .enable_reg = 0x30e4,
1214 .enable_mask = BIT(0),
1225 .halt_reg = 0x30d4,
1227 .enable_reg = 0x30d4,
1228 .enable_mask = BIT(0),
1239 .halt_reg = 0x3128,
1241 .enable_reg = 0x3128,
1242 .enable_mask = BIT(0),
1254 .halt_reg = 0x3124,
1256 .enable_reg = 0x3124,
1257 .enable_mask = BIT(0),
1268 .halt_reg = 0x3134,
1270 .enable_reg = 0x3134,
1271 .enable_mask = BIT(0),
1282 .halt_reg = 0x3154,
1284 .enable_reg = 0x3154,
1285 .enable_mask = BIT(0),
1296 .halt_reg = 0x3144,
1298 .enable_reg = 0x3144,
1299 .enable_mask = BIT(0),
1310 .halt_reg = 0x3188,
1312 .enable_reg = 0x3188,
1313 .enable_mask = BIT(0),
1325 .halt_reg = 0x3184,
1327 .enable_reg = 0x3184,
1328 .enable_mask = BIT(0),
1339 .halt_reg = 0x3194,
1341 .enable_reg = 0x3194,
1342 .enable_mask = BIT(0),
1353 .halt_reg = 0x31b4,
1355 .enable_reg = 0x31b4,
1356 .enable_mask = BIT(0),
1367 .halt_reg = 0x31a4,
1369 .enable_reg = 0x31a4,
1370 .enable_mask = BIT(0),
1381 .halt_reg = 0x31e8,
1383 .enable_reg = 0x31e8,
1384 .enable_mask = BIT(0),
1396 .halt_reg = 0x31e4,
1398 .enable_reg = 0x31e4,
1399 .enable_mask = BIT(0),
1410 .halt_reg = 0x31f4,
1412 .enable_reg = 0x31f4,
1413 .enable_mask = BIT(0),
1424 .halt_reg = 0x3214,
1426 .enable_reg = 0x3214,
1427 .enable_mask = BIT(0),
1438 .halt_reg = 0x3204,
1440 .enable_reg = 0x3204,
1441 .enable_mask = BIT(0),
1452 .halt_reg = 0x3704,
1454 .enable_reg = 0x3704,
1455 .enable_mask = BIT(0),
1466 .halt_reg = 0x3714,
1468 .enable_reg = 0x3714,
1469 .enable_mask = BIT(0),
1480 .halt_reg = 0x3444,
1482 .enable_reg = 0x3444,
1483 .enable_mask = BIT(0),
1494 .halt_reg = 0x3474,
1496 .enable_reg = 0x3474,
1497 .enable_mask = BIT(0),
1508 .halt_reg = 0x3224,
1510 .enable_reg = 0x3224,
1511 .enable_mask = BIT(0),
1523 .halt_reg = 0x35c0,
1525 .enable_reg = 0x35c0,
1526 .enable_mask = BIT(0),
1537 .halt_reg = 0x35a8,
1539 .enable_reg = 0x35a8,
1540 .enable_mask = BIT(0),
1551 .halt_reg = 0x35ac,
1553 .enable_reg = 0x35ac,
1554 .enable_mask = BIT(0),
1565 .halt_reg = 0x35b0,
1567 .enable_reg = 0x35b0,
1568 .enable_mask = BIT(0),
1579 .halt_reg = 0x35b4,
1581 .enable_reg = 0x35b4,
1582 .enable_mask = BIT(0),
1594 .halt_reg = 0x35b8,
1596 .enable_reg = 0x35b8,
1597 .enable_mask = BIT(0),
1608 .halt_reg = 0x3384,
1610 .enable_reg = 0x3384,
1611 .enable_mask = BIT(0),
1622 .halt_reg = 0x33b4,
1624 .enable_reg = 0x33b4,
1625 .enable_mask = BIT(0),
1636 .halt_reg = 0x33e4,
1638 .enable_reg = 0x33e4,
1639 .enable_mask = BIT(0),
1650 .halt_reg = 0x3414,
1652 .enable_reg = 0x3414,
1653 .enable_mask = BIT(0),
1664 .halt_reg = 0x3494,
1666 .enable_reg = 0x3494,
1667 .enable_mask = BIT(0),
1679 .halt_reg = 0x3024,
1681 .enable_reg = 0x3024,
1682 .enable_mask = BIT(0),
1693 .halt_reg = 0x3054,
1695 .enable_reg = 0x3054,
1696 .enable_mask = BIT(0),
1707 .halt_reg = 0x3084,
1709 .enable_reg = 0x3084,
1710 .enable_mask = BIT(0),
1721 .halt_reg = 0x3484,
1723 .enable_reg = 0x3484,
1724 .enable_mask = BIT(0),
1736 .halt_reg = 0x36a8,
1738 .enable_reg = 0x36a8,
1739 .enable_mask = BIT(0),
1750 .halt_reg = 0x36ac,
1752 .enable_reg = 0x36ac,
1753 .enable_mask = BIT(0),
1764 .halt_reg = 0x36b8,
1766 .enable_reg = 0x36b8,
1767 .enable_mask = BIT(0),
1779 .halt_reg = 0x36bc,
1781 .enable_reg = 0x36bc,
1782 .enable_mask = BIT(0),
1793 .halt_reg = 0x3b74,
1795 .enable_reg = 0x3b74,
1796 .enable_mask = BIT(0),
1807 .halt_reg = 0x3b70,
1809 .enable_reg = 0x3b70,
1810 .enable_mask = BIT(0),
1821 .halt_reg = 0x3b68,
1823 .enable_reg = 0x3b68,
1824 .enable_mask = BIT(0),
1835 .halt_reg = 0x3b6c,
1837 .enable_reg = 0x3b6c,
1838 .enable_mask = BIT(0),
1849 .halt_reg = 0x2308,
1852 .enable_reg = 0x2308,
1853 .enable_mask = BIT(0),
1865 .halt_reg = 0x2310,
1867 .enable_reg = 0x2310,
1868 .enable_mask = BIT(0),
1880 .halt_reg = 0x233c,
1882 .enable_reg = 0x233c,
1883 .enable_mask = BIT(0),
1895 .halt_reg = 0x2340,
1897 .enable_reg = 0x2340,
1898 .enable_mask = BIT(0),
1910 .halt_reg = 0x2344,
1912 .enable_reg = 0x2344,
1913 .enable_mask = BIT(0),
1925 .halt_reg = 0x2348,
1927 .enable_reg = 0x2348,
1928 .enable_mask = BIT(0),
1940 .halt_reg = 0x2324,
1942 .enable_reg = 0x2324,
1943 .enable_mask = BIT(0),
1955 .halt_reg = 0x230c,
1957 .enable_reg = 0x230c,
1958 .enable_mask = BIT(0),
1970 .halt_reg = 0x2338,
1972 .enable_reg = 0x2338,
1973 .enable_mask = BIT(0),
1985 .halt_reg = 0x231c,
1987 .enable_reg = 0x231c,
1988 .enable_mask = BIT(0),
2000 .halt_reg = 0x2314,
2002 .enable_reg = 0x2314,
2003 .enable_mask = BIT(0),
2015 .halt_reg = 0x2318,
2017 .enable_reg = 0x2318,
2018 .enable_mask = BIT(0),
2030 .halt_reg = 0x2328,
2032 .enable_reg = 0x2328,
2033 .enable_mask = BIT(0),
2045 .halt_reg = 0x502c,
2047 .enable_reg = 0x502c,
2048 .enable_mask = BIT(0),
2060 .halt_reg = 0x506c,
2062 .enable_reg = 0x506c,
2063 .enable_mask = BIT(0),
2076 .halt_reg = 0x5064,
2078 .enable_reg = 0x5064,
2079 .enable_mask = BIT(0),
2091 .halt_reg = 0x4058,
2093 .enable_reg = 0x4058,
2094 .enable_mask = BIT(0),
2106 .halt_reg = 0x4028,
2108 .enable_reg = 0x4028,
2109 .enable_mask = BIT(0),
2124 .halt_reg = 0x40b0,
2126 .enable_reg = 0x40b0,
2127 .enable_mask = BIT(0),
2139 .halt_reg = 0x403c,
2141 .enable_reg = 0x403c,
2142 .enable_mask = BIT(0),
2154 .halt_reg = 0x1030,
2156 .enable_reg = 0x1030,
2157 .enable_mask = BIT(0),
2169 .halt_reg = 0x1034,
2171 .enable_reg = 0x1034,
2172 .enable_mask = BIT(0),
2183 .halt_reg = 0x1038,
2185 .enable_reg = 0x1038,
2186 .enable_mask = BIT(0),
2198 .halt_reg = 0x1028,
2200 .enable_reg = 0x1028,
2201 .enable_mask = BIT(0),
2213 .halt_reg = 0x1048,
2215 .enable_reg = 0x1048,
2216 .enable_mask = BIT(0),
2228 .halt_reg = 0x104c,
2230 .enable_reg = 0x104c,
2231 .enable_mask = BIT(0),
2243 .halt_reg = 0x1054,
2245 .enable_reg = 0x1054,
2246 .enable_mask = BIT(0),
2258 .gdscr = 0x1024,
2259 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2268 .gdscr = 0x1040,
2269 .cxcs = (unsigned int []){ 0x1048 },
2279 .gdscr = 0x1044,
2280 .cxcs = (unsigned int []){ 0x104c },
2290 .gdscr = 0x1050,
2291 .cxcs = (unsigned int []){ 0x1054 },
2301 .gdscr = 0x2304,
2302 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2311 .gdscr = 0x34a0,
2312 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2321 .gdscr = 0x35a4,
2322 .cxcs = (unsigned int []){ 0x35a8 },
2332 .gdscr = 0x36a4,
2333 .cxcs = (unsigned int []){ 0x36bc },
2343 .gdscr = 0x36d4,
2344 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2354 .gdscr = 0x3b64,
2355 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2363 .gdscr = 0x4034,
2372 .gdscr = 0x4024,
2373 .cxcs = (unsigned int []){ 0x4028 },
2530 [CAMSS_MICRO_BCR] = { 0x3490 },
2537 .max_register = 0x5200,