Lines Matching +full:0 +full:x4038
45 .l_reg = 0x0004,
46 .m_reg = 0x0008,
47 .n_reg = 0x000c,
48 .config_reg = 0x0014,
49 .mode_reg = 0x0000,
50 .status_reg = 0x001c,
63 .enable_reg = 0x0100,
64 .enable_mask = BIT(0),
76 .l_reg = 0x0044,
77 .m_reg = 0x0048,
78 .n_reg = 0x004c,
79 .config_reg = 0x0050,
80 .mode_reg = 0x0040,
81 .status_reg = 0x005c,
94 .enable_reg = 0x0100,
107 .l_reg = 0x4104,
108 .m_reg = 0x4108,
109 .n_reg = 0x410c,
110 .config_reg = 0x4110,
111 .mode_reg = 0x4100,
112 .status_reg = 0x411c,
124 .l_reg = 0x0084,
125 .m_reg = 0x0088,
126 .n_reg = 0x008c,
127 .config_reg = 0x0090,
128 .mode_reg = 0x0080,
129 .status_reg = 0x009c,
142 { P_XO, 0 },
156 { P_XO, 0 },
174 { P_XO, 0 },
190 { P_XO, 0 },
206 { P_XO, 0 },
224 { P_XO, 0 },
242 { P_XO, 0 },
260 .cmd_rcgr = 0x5000,
272 F(19200000, P_XO, 1, 0, 0),
273 F(37500000, P_GPLL0, 16, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
275 F(75000000, P_GPLL0, 8, 0, 0),
276 F(100000000, P_GPLL0, 6, 0, 0),
277 F(150000000, P_GPLL0, 4, 0, 0),
278 F(200000000, P_MMPLL0, 4, 0, 0),
279 F(266666666, P_MMPLL0, 3, 0, 0),
284 F( 19200000, P_XO, 1, 0, 0),
285 F( 37500000, P_GPLL0, 16, 0, 0),
286 F( 50000000, P_GPLL0, 12, 0, 0),
287 F( 75000000, P_GPLL0, 8, 0, 0),
288 F(100000000, P_GPLL0, 6, 0, 0),
289 F(150000000, P_GPLL0, 4, 0, 0),
290 F(291750000, P_MMPLL1, 4, 0, 0),
291 F(400000000, P_MMPLL0, 2, 0, 0),
292 F(466800000, P_MMPLL1, 2.5, 0, 0),
297 .cmd_rcgr = 0x5040,
310 F( 19200000, P_XO, 1, 0, 0),
311 F( 37500000, P_GPLL0, 16, 0, 0),
312 F( 50000000, P_GPLL0, 12, 0, 0),
313 F( 75000000, P_GPLL0, 8, 0, 0),
314 F(100000000, P_GPLL0, 6, 0, 0),
315 F(150000000, P_GPLL0, 4, 0, 0),
316 F(291750000, P_MMPLL1, 4, 0, 0),
317 F(400000000, P_MMPLL0, 2, 0, 0),
322 .cmd_rcgr = 0x5090,
335 F(100000000, P_GPLL0, 6, 0, 0),
336 F(200000000, P_MMPLL0, 4, 0, 0),
341 .cmd_rcgr = 0x3090,
354 .cmd_rcgr = 0x3100,
367 .cmd_rcgr = 0x3160,
380 .cmd_rcgr = 0x31c0,
393 F(37500000, P_GPLL0, 16, 0, 0),
394 F(50000000, P_GPLL0, 12, 0, 0),
395 F(60000000, P_GPLL0, 10, 0, 0),
396 F(80000000, P_GPLL0, 7.5, 0, 0),
397 F(100000000, P_GPLL0, 6, 0, 0),
398 F(109090000, P_GPLL0, 5.5, 0, 0),
399 F(133330000, P_GPLL0, 4.5, 0, 0),
400 F(150000000, P_GPLL0, 4, 0, 0),
401 F(200000000, P_GPLL0, 3, 0, 0),
402 F(228570000, P_MMPLL0, 3.5, 0, 0),
403 F(266670000, P_MMPLL0, 3, 0, 0),
404 F(320000000, P_MMPLL0, 2.5, 0, 0),
405 F(400000000, P_MMPLL0, 2, 0, 0),
410 F(37500000, P_GPLL0, 16, 0, 0),
411 F(50000000, P_GPLL0, 12, 0, 0),
412 F(60000000, P_GPLL0, 10, 0, 0),
413 F(80000000, P_GPLL0, 7.5, 0, 0),
414 F(100000000, P_GPLL0, 6, 0, 0),
415 F(109090000, P_GPLL0, 5.5, 0, 0),
416 F(133330000, P_GPLL0, 4.5, 0, 0),
417 F(200000000, P_GPLL0, 3, 0, 0),
418 F(228570000, P_MMPLL0, 3.5, 0, 0),
419 F(266670000, P_MMPLL0, 3, 0, 0),
420 F(320000000, P_MMPLL0, 2.5, 0, 0),
421 F(400000000, P_MMPLL0, 2, 0, 0),
422 F(465000000, P_MMPLL3, 2, 0, 0),
427 .cmd_rcgr = 0x3600,
440 .cmd_rcgr = 0x3620,
453 F(37500000, P_GPLL0, 16, 0, 0),
454 F(60000000, P_GPLL0, 10, 0, 0),
455 F(75000000, P_GPLL0, 8, 0, 0),
456 F(92310000, P_GPLL0, 6.5, 0, 0),
457 F(100000000, P_GPLL0, 6, 0, 0),
458 F(133330000, P_MMPLL0, 6, 0, 0),
459 F(177780000, P_MMPLL0, 4.5, 0, 0),
460 F(200000000, P_MMPLL0, 4, 0, 0),
465 F(37500000, P_GPLL0, 16, 0, 0),
466 F(60000000, P_GPLL0, 10, 0, 0),
467 F(75000000, P_GPLL0, 8, 0, 0),
468 F(85710000, P_GPLL0, 7, 0, 0),
469 F(100000000, P_GPLL0, 6, 0, 0),
470 F(133330000, P_MMPLL0, 6, 0, 0),
471 F(160000000, P_MMPLL0, 5, 0, 0),
472 F(200000000, P_MMPLL0, 4, 0, 0),
473 F(228570000, P_MMPLL0, 3.5, 0, 0),
474 F(240000000, P_GPLL0, 2.5, 0, 0),
475 F(266670000, P_MMPLL0, 3, 0, 0),
476 F(320000000, P_MMPLL0, 2.5, 0, 0),
481 .cmd_rcgr = 0x2040,
494 F(75000000, P_GPLL0, 8, 0, 0),
495 F(133330000, P_GPLL0, 4.5, 0, 0),
496 F(200000000, P_GPLL0, 3, 0, 0),
497 F(228570000, P_MMPLL0, 3.5, 0, 0),
498 F(266670000, P_MMPLL0, 3, 0, 0),
499 F(320000000, P_MMPLL0, 2.5, 0, 0),
504 .cmd_rcgr = 0x3500,
517 .cmd_rcgr = 0x3520,
530 .cmd_rcgr = 0x3540,
543 .cmd_rcgr = 0x2000,
557 .cmd_rcgr = 0x2020,
571 F(66700000, P_GPLL0, 9, 0, 0),
572 F(100000000, P_GPLL0, 6, 0, 0),
573 F(133330000, P_MMPLL0, 6, 0, 0),
574 F(160000000, P_MMPLL0, 5, 0, 0),
579 F(50000000, P_GPLL0, 12, 0, 0),
580 F(100000000, P_GPLL0, 6, 0, 0),
581 F(133330000, P_MMPLL0, 6, 0, 0),
582 F(200000000, P_MMPLL0, 4, 0, 0),
583 F(266670000, P_MMPLL0, 3, 0, 0),
584 F(465000000, P_MMPLL3, 2, 0, 0),
589 .cmd_rcgr = 0x1000,
603 F(19200000, P_XO, 1, 0, 0),
608 .cmd_rcgr = 0x3300,
631 .cmd_rcgr = 0x3420,
645 .cmd_rcgr = 0x3450,
659 F(19200000, P_XO, 1, 0, 0),
661 F(66670000, P_GPLL0, 9, 0, 0),
666 F(4800000, P_XO, 4, 0, 0),
669 F(9600000, P_XO, 2, 0, 0),
671 F(19200000, P_XO, 1, 0, 0),
674 F(48000000, P_GPLL0, 12.5, 0, 0),
675 F(64000000, P_MMPLL0, 12.5, 0, 0),
676 F(66670000, P_GPLL0, 9, 0, 0),
681 .cmd_rcgr = 0x3360,
694 .cmd_rcgr = 0x3390,
707 .cmd_rcgr = 0x33c0,
720 .cmd_rcgr = 0x33f0,
733 F(100000000, P_GPLL0, 6, 0, 0),
734 F(200000000, P_MMPLL0, 4, 0, 0),
739 .cmd_rcgr = 0x3000,
752 .cmd_rcgr = 0x3030,
765 .cmd_rcgr = 0x3060,
778 F(133330000, P_GPLL0, 4.5, 0, 0),
779 F(150000000, P_GPLL0, 4, 0, 0),
780 F(266670000, P_MMPLL0, 3, 0, 0),
781 F(320000000, P_MMPLL0, 2.5, 0, 0),
782 F(400000000, P_MMPLL0, 2, 0, 0),
787 F(133330000, P_GPLL0, 4.5, 0, 0),
788 F(266670000, P_MMPLL0, 3, 0, 0),
789 F(320000000, P_MMPLL0, 2.5, 0, 0),
790 F(400000000, P_MMPLL0, 2, 0, 0),
791 F(465000000, P_MMPLL3, 2, 0, 0),
796 .cmd_rcgr = 0x3640,
814 .cmd_rcgr = 0x2120,
828 .cmd_rcgr = 0x2140,
842 F(19200000, P_XO, 1, 0, 0),
847 .cmd_rcgr = 0x20e0,
860 F(135000000, P_EDPLINK, 2, 0, 0),
861 F(270000000, P_EDPLINK, 11, 0, 0),
866 .cmd_rcgr = 0x20c0,
885 .cmd_rcgr = 0x20a0,
899 F(19200000, P_XO, 1, 0, 0),
904 .cmd_rcgr = 0x2160,
917 .cmd_rcgr = 0x2180,
935 .cmd_rcgr = 0x2060,
949 F(19200000, P_XO, 1, 0, 0),
954 .cmd_rcgr = 0x2100,
967 F(19200000, P_XO, 1, 0, 0),
972 .cmd_rcgr = 0x2080,
985 .halt_reg = 0x3348,
987 .enable_reg = 0x3348,
988 .enable_mask = BIT(0),
1001 .halt_reg = 0x3344,
1003 .enable_reg = 0x3344,
1004 .enable_mask = BIT(0),
1018 .halt_reg = 0x30bc,
1020 .enable_reg = 0x30bc,
1021 .enable_mask = BIT(0),
1034 .halt_reg = 0x30b4,
1036 .enable_reg = 0x30b4,
1037 .enable_mask = BIT(0),
1051 .halt_reg = 0x30c4,
1053 .enable_reg = 0x30c4,
1054 .enable_mask = BIT(0),
1068 .halt_reg = 0x30e4,
1070 .enable_reg = 0x30e4,
1071 .enable_mask = BIT(0),
1085 .halt_reg = 0x30d4,
1087 .enable_reg = 0x30d4,
1088 .enable_mask = BIT(0),
1102 .halt_reg = 0x3128,
1104 .enable_reg = 0x3128,
1105 .enable_mask = BIT(0),
1118 .halt_reg = 0x3124,
1120 .enable_reg = 0x3124,
1121 .enable_mask = BIT(0),
1135 .halt_reg = 0x3134,
1137 .enable_reg = 0x3134,
1138 .enable_mask = BIT(0),
1152 .halt_reg = 0x3154,
1154 .enable_reg = 0x3154,
1155 .enable_mask = BIT(0),
1169 .halt_reg = 0x3144,
1171 .enable_reg = 0x3144,
1172 .enable_mask = BIT(0),
1186 .halt_reg = 0x3188,
1188 .enable_reg = 0x3188,
1189 .enable_mask = BIT(0),
1202 .halt_reg = 0x3184,
1204 .enable_reg = 0x3184,
1205 .enable_mask = BIT(0),
1219 .halt_reg = 0x3194,
1221 .enable_reg = 0x3194,
1222 .enable_mask = BIT(0),
1236 .halt_reg = 0x31b4,
1238 .enable_reg = 0x31b4,
1239 .enable_mask = BIT(0),
1253 .halt_reg = 0x31a4,
1255 .enable_reg = 0x31a4,
1256 .enable_mask = BIT(0),
1270 .halt_reg = 0x31e8,
1272 .enable_reg = 0x31e8,
1273 .enable_mask = BIT(0),
1286 .halt_reg = 0x31e4,
1288 .enable_reg = 0x31e4,
1289 .enable_mask = BIT(0),
1303 .halt_reg = 0x31f4,
1305 .enable_reg = 0x31f4,
1306 .enable_mask = BIT(0),
1320 .halt_reg = 0x3214,
1322 .enable_reg = 0x3214,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x3204,
1339 .enable_reg = 0x3204,
1340 .enable_mask = BIT(0),
1354 .halt_reg = 0x3704,
1356 .enable_reg = 0x3704,
1357 .enable_mask = BIT(0),
1371 .halt_reg = 0x3714,
1373 .enable_reg = 0x3714,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x3444,
1390 .enable_reg = 0x3444,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0x3474,
1407 .enable_reg = 0x3474,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x3224,
1424 .enable_reg = 0x3224,
1425 .enable_mask = BIT(0),
1438 .halt_reg = 0x35a8,
1440 .enable_reg = 0x35a8,
1441 .enable_mask = BIT(0),
1455 .halt_reg = 0x35ac,
1457 .enable_reg = 0x35ac,
1458 .enable_mask = BIT(0),
1472 .halt_reg = 0x35b0,
1474 .enable_reg = 0x35b0,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0x35b4,
1491 .enable_reg = 0x35b4,
1492 .enable_mask = BIT(0),
1505 .halt_reg = 0x35b8,
1507 .enable_reg = 0x35b8,
1508 .enable_mask = BIT(0),
1521 .halt_reg = 0x35bc,
1523 .enable_reg = 0x35bc,
1524 .enable_mask = BIT(0),
1538 .halt_reg = 0x3384,
1540 .enable_reg = 0x3384,
1541 .enable_mask = BIT(0),
1555 .halt_reg = 0x33b4,
1557 .enable_reg = 0x33b4,
1558 .enable_mask = BIT(0),
1572 .halt_reg = 0x33e4,
1574 .enable_reg = 0x33e4,
1575 .enable_mask = BIT(0),
1589 .halt_reg = 0x3414,
1591 .enable_reg = 0x3414,
1592 .enable_mask = BIT(0),
1606 .halt_reg = 0x3494,
1608 .enable_reg = 0x3494,
1609 .enable_mask = BIT(0),
1622 .halt_reg = 0x3024,
1624 .enable_reg = 0x3024,
1625 .enable_mask = BIT(0),
1639 .halt_reg = 0x3054,
1641 .enable_reg = 0x3054,
1642 .enable_mask = BIT(0),
1656 .halt_reg = 0x3084,
1658 .enable_reg = 0x3084,
1659 .enable_mask = BIT(0),
1673 .halt_reg = 0x3484,
1675 .enable_reg = 0x3484,
1676 .enable_mask = BIT(0),
1689 .halt_reg = 0x36b4,
1691 .enable_reg = 0x36b4,
1692 .enable_mask = BIT(0),
1705 .halt_reg = 0x36b0,
1707 .enable_reg = 0x36b0,
1708 .enable_mask = BIT(0),
1722 .halt_reg = 0x36a8,
1724 .enable_reg = 0x36a8,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x36ac,
1741 .enable_reg = 0x36ac,
1742 .enable_mask = BIT(0),
1756 .halt_reg = 0x36b8,
1758 .enable_reg = 0x36b8,
1759 .enable_mask = BIT(0),
1772 .halt_reg = 0x36bc,
1774 .enable_reg = 0x36bc,
1775 .enable_mask = BIT(0),
1788 .halt_reg = 0x36c0,
1790 .enable_reg = 0x36c0,
1791 .enable_mask = BIT(0),
1805 .halt_reg = 0x2308,
1807 .enable_reg = 0x2308,
1808 .enable_mask = BIT(0),
1821 .halt_reg = 0x2310,
1823 .enable_reg = 0x2310,
1824 .enable_mask = BIT(0),
1838 .halt_reg = 0x233c,
1840 .enable_reg = 0x233c,
1841 .enable_mask = BIT(0),
1855 .halt_reg = 0x2340,
1857 .enable_reg = 0x2340,
1858 .enable_mask = BIT(0),
1872 .halt_reg = 0x2334,
1874 .enable_reg = 0x2334,
1875 .enable_mask = BIT(0),
1889 .halt_reg = 0x2330,
1891 .enable_reg = 0x2330,
1892 .enable_mask = BIT(0),
1906 .halt_reg = 0x232c,
1908 .enable_reg = 0x232c,
1909 .enable_mask = BIT(0),
1923 .halt_reg = 0x2344,
1925 .enable_reg = 0x2344,
1926 .enable_mask = BIT(0),
1940 .halt_reg = 0x2348,
1942 .enable_reg = 0x2348,
1943 .enable_mask = BIT(0),
1957 .halt_reg = 0x2324,
1959 .enable_reg = 0x2324,
1960 .enable_mask = BIT(0),
1974 .halt_reg = 0x230c,
1976 .enable_reg = 0x230c,
1977 .enable_mask = BIT(0),
1990 .halt_reg = 0x2338,
1992 .enable_reg = 0x2338,
1993 .enable_mask = BIT(0),
2007 .halt_reg = 0x231c,
2009 .enable_reg = 0x231c,
2010 .enable_mask = BIT(0),
2024 .halt_reg = 0x2320,
2026 .enable_reg = 0x2320,
2027 .enable_mask = BIT(0),
2041 .halt_reg = 0x2314,
2043 .enable_reg = 0x2314,
2044 .enable_mask = BIT(0),
2058 .halt_reg = 0x2318,
2060 .enable_reg = 0x2318,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0x2328,
2077 .enable_reg = 0x2328,
2078 .enable_mask = BIT(0),
2092 .halt_reg = 0x502c,
2094 .enable_reg = 0x502c,
2095 .enable_mask = BIT(0),
2108 .halt_reg = 0x5024,
2110 .enable_reg = 0x5024,
2111 .enable_mask = BIT(0),
2125 .halt_reg = 0x5028,
2127 .enable_reg = 0x5028,
2128 .enable_mask = BIT(0),
2142 .halt_reg = 0x506c,
2144 .enable_reg = 0x506c,
2145 .enable_mask = BIT(0),
2159 .halt_reg = 0x5064,
2161 .enable_reg = 0x5064,
2162 .enable_mask = BIT(0),
2176 .halt_reg = 0x4058,
2178 .enable_reg = 0x4058,
2179 .enable_mask = BIT(0),
2193 .halt_reg = 0x50b4,
2195 .enable_reg = 0x50b4,
2196 .enable_mask = BIT(0),
2210 .halt_reg = 0x4028,
2212 .enable_reg = 0x4028,
2213 .enable_mask = BIT(0),
2227 .halt_reg = 0x403c,
2229 .enable_reg = 0x403c,
2230 .enable_mask = BIT(0),
2243 .halt_reg = 0x4038,
2245 .enable_reg = 0x4038,
2246 .enable_mask = BIT(0),
2259 .halt_reg = 0x1030,
2261 .enable_reg = 0x1030,
2262 .enable_mask = BIT(0),
2275 .halt_reg = 0x1034,
2277 .enable_reg = 0x1034,
2278 .enable_mask = BIT(0),
2291 .halt_reg = 0x1038,
2293 .enable_reg = 0x1038,
2294 .enable_mask = BIT(0),
2308 .halt_reg = 0x1028,
2310 .enable_reg = 0x1028,
2311 .enable_mask = BIT(0),
2328 .vco_val = 0x0,
2329 .vco_mask = 0x3 << 20,
2330 .pre_div_val = 0x0,
2331 .pre_div_mask = 0x7 << 12,
2332 .post_div_val = 0x0,
2333 .post_div_mask = 0x3 << 8,
2335 .main_output_mask = BIT(0),
2342 .vco_val = 0x0,
2343 .vco_mask = 0x3 << 20,
2344 .pre_div_val = 0x0,
2345 .pre_div_mask = 0x7 << 12,
2346 .post_div_val = 0x0,
2347 .post_div_mask = 0x3 << 8,
2349 .main_output_mask = BIT(0),
2354 .gdscr = 0x1024,
2355 .cxcs = (unsigned int []){ 0x1028 },
2366 .gdscr = 0x2304,
2367 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2376 .gdscr = 0x35a4,
2377 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2386 .gdscr = 0x36a4,
2387 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2396 .gdscr = 0x4024,
2397 .cxcs = (unsigned int []){ 0x4028 },
2406 .gdscr = 0x4034,
2415 .gdscr = 0x4034,
2416 .cxcs = (unsigned int []){ 0x4028 },
2501 [SPDM_RESET] = { 0x0200 },
2502 [SPDM_RM_RESET] = { 0x0300 },
2503 [VENUS0_RESET] = { 0x1020 },
2504 [MDSS_RESET] = { 0x2300 },
2519 .max_register = 0x5104,
2660 [SPDM_RESET] = { 0x0200 },
2661 [SPDM_RM_RESET] = { 0x0300 },
2662 [VENUS0_RESET] = { 0x1020 },
2663 [MDSS_RESET] = { 0x2300 },
2664 [CAMSS_PHY0_RESET] = { 0x3020 },
2665 [CAMSS_PHY1_RESET] = { 0x3050 },
2666 [CAMSS_PHY2_RESET] = { 0x3080 },
2667 [CAMSS_CSI0_RESET] = { 0x30b0 },
2668 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2669 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2670 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2671 [CAMSS_CSI1_RESET] = { 0x3120 },
2672 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2673 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2674 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2675 [CAMSS_CSI2_RESET] = { 0x3180 },
2676 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2677 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2678 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2679 [CAMSS_CSI3_RESET] = { 0x31e0 },
2680 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2681 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2682 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2683 [CAMSS_ISPIF_RESET] = { 0x3220 },
2684 [CAMSS_CCI_RESET] = { 0x3340 },
2685 [CAMSS_MCLK0_RESET] = { 0x3380 },
2686 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2687 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2688 [CAMSS_MCLK3_RESET] = { 0x3410 },
2689 [CAMSS_GP0_RESET] = { 0x3440 },
2690 [CAMSS_GP1_RESET] = { 0x3470 },
2691 [CAMSS_TOP_RESET] = { 0x3480 },
2692 [CAMSS_MICRO_RESET] = { 0x3490 },
2693 [CAMSS_JPEG_RESET] = { 0x35a0 },
2694 [CAMSS_VFE_RESET] = { 0x36a0 },
2695 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2696 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2697 [OXILI_RESET] = { 0x4020 },
2698 [OXILICX_RESET] = { 0x4030 },
2699 [OCMEMCX_RESET] = { 0x4050 },
2700 [MMSS_RBCRP_RESET] = { 0x4080 },
2701 [MMSSNOCAHB_RESET] = { 0x5020 },
2702 [MMSSNOCAXI_RESET] = { 0x5060 },
2703 [OCMEMNOC_RESET] = { 0x50b0 },
2719 .max_register = 0x5104,