Lines Matching +full:0 +full:x1004

31 	{ 249600000, 2000000000, 0 },
35 	.l = 0x1a,
36 	.alpha = 0xaaa,
37 	.config_ctl_val = 0x20485699,
38 	.config_ctl_hi_val = 0x00002267,
39 	.config_ctl_hi1_val = 0x00000024,
40 	.test_ctl_val = 0x00000000,
41 	.test_ctl_hi_val = 0x00000000,
42 	.test_ctl_hi1_val = 0x00000020,
43 	.user_ctl_val = 0x00000000,
44 	.user_ctl_hi_val = 0x00000805,
45 	.user_ctl_hi1_val = 0x000000d0,
49 	.offset = 0x100,
66 	{ P_BI_TCXO, 0 },
80 	F(19200000, P_BI_TCXO, 1, 0, 0),
81 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
82 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
87 	F(19200000, P_BI_TCXO, 1, 0, 0),
88 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
89 	F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
90 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
95 	.cmd_rcgr = 0x1120,
96 	.mnd_width = 0,
110 	.halt_reg = 0x1078,
113 		.enable_reg = 0x1078,
114 		.enable_mask = BIT(0),
123 	.halt_reg = 0x107c,
126 		.enable_reg = 0x107c,
127 		.enable_mask = BIT(0),
136 	.halt_reg = 0x1088,
139 		.enable_reg = 0x1088,
140 		.enable_mask = BIT(0),
149 	.halt_reg = 0x1098,
152 		.enable_reg = 0x1098,
153 		.enable_mask = BIT(0),
167 	.halt_reg = 0x108c,
170 		.enable_reg = 0x108c,
171 		.enable_mask = BIT(0),
180 	.halt_reg = 0x1004,
183 		.enable_reg = 0x1004,
184 		.enable_mask = BIT(0),
193 	.halt_reg = 0x109c,
196 		.enable_reg = 0x109c,
197 		.enable_mask = BIT(0),
206 	.halt_reg = 0x1064,
209 		.enable_reg = 0x1064,
210 		.enable_mask = BIT(0),
224 	.gdscr = 0x106c,
225 	.gds_hw_ctrl = 0x1540,
234 	.gdscr = 0x100c,
235 	.clamp_io_ctrl = 0x1508,
258 	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
259 	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
260 	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
261 	[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
262 	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
274 	.max_register	= 0x8008,