Lines Matching +full:0 +full:x10b0
38 .halt_reg = 0x1020,
40 .enable_reg = 0x1020,
41 .enable_mask = BIT(0),
55 { 1000000000, 2000000000, 0 },
61 .offset = 0x0,
76 .offset = 0x40,
91 { P_GPU_XO, 0 },
107 .cmd_rcgr = 0x1070,
108 .mnd_width = 0,
127 .halt_reg = 0x1098,
129 .hwcg_reg = 0x1098,
132 .enable_reg = 0x1098,
133 .enable_mask = BIT(0),
147 { P_GPU_XO, 0 },
159 F(19200000, P_GPU_XO, 1, 0, 0),
164 .cmd_rcgr = 0x10b0,
165 .mnd_width = 0,
178 F(19200000, P_GPU_XO, 1, 0, 0),
179 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
184 .cmd_rcgr = 0x1030,
185 .mnd_width = 0,
198 .halt_reg = 0x10d0,
201 .enable_reg = 0x10d0,
202 .enable_mask = BIT(0),
216 .halt_reg = 0x1054,
219 .enable_reg = 0x1054,
220 .enable_mask = BIT(0),
234 .gdscr = 0x1004,
235 .gds_hw_ctrl = 0x1008,
244 .gdscr = 0x1094,
245 .clamp_io_ctrl = 0x130,
248 .cxcs = (unsigned int []){ 0x1098 },
264 [GPU_CX_BCR] = { 0x1000 },
265 [RBCPR_BCR] = { 0x1050 },
266 [GPU_GX_BCR] = { 0x1090 },
267 [SPDM_BCR] = { 0x10E0 },
286 .max_register = 0x9034,
311 .config_ctl_val = 0x4001055b, in gpucc_sdm660_probe()
312 .alpha = 0xaaaaab00, in gpucc_sdm660_probe()
314 .vco_val = 0x2 << 20, in gpucc_sdm660_probe()
315 .vco_mask = 0x3 << 20, in gpucc_sdm660_probe()
316 .main_output_mask = 0x1, in gpucc_sdm660_probe()
324 gpu_pll_config.l = 0x29; in gpucc_sdm660_probe()
325 gpu_pll_config.alpha_hi = 0xaa; in gpucc_sdm660_probe()
329 gpu_pll_config.l = 0x26; in gpucc_sdm660_probe()
330 gpu_pll_config.alpha_hi = 0x8a; in gpucc_sdm660_probe()