Lines Matching +full:0 +full:x1020
37 .halt_reg = 0x1020,
39 .enable_reg = 0x1020,
40 .enable_mask = BIT(0),
54 { 1000000000, 2000000000, 0 },
60 .offset = 0x0,
75 .offset = 0x40,
90 { P_GPU_XO, 0 },
106 .cmd_rcgr = 0x1070,
107 .mnd_width = 0,
126 .halt_reg = 0x1098,
128 .hwcg_reg = 0x1098,
131 .enable_reg = 0x1098,
132 .enable_mask = BIT(0),
146 { P_GPU_XO, 0 },
158 F(19200000, P_GPU_XO, 1, 0, 0),
163 .cmd_rcgr = 0x10b0,
164 .mnd_width = 0,
177 F(19200000, P_GPU_XO, 1, 0, 0),
178 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
183 .cmd_rcgr = 0x1030,
184 .mnd_width = 0,
197 .halt_reg = 0x10d0,
200 .enable_reg = 0x10d0,
201 .enable_mask = BIT(0),
215 .halt_reg = 0x1054,
218 .enable_reg = 0x1054,
219 .enable_mask = BIT(0),
233 .gdscr = 0x1004,
234 .gds_hw_ctrl = 0x1008,
243 .gdscr = 0x1094,
244 .clamp_io_ctrl = 0x130,
247 .cxcs = (unsigned int []){ 0x1098 },
263 [GPU_CX_BCR] = { 0x1000 },
264 [RBCPR_BCR] = { 0x1050 },
265 [GPU_GX_BCR] = { 0x1090 },
266 [SPDM_BCR] = { 0x10E0 },
285 .max_register = 0x9034,
310 .config_ctl_val = 0x4001055b,
311 .alpha = 0xaaaaab00,
313 .vco_val = 0x2 << 20,
314 .vco_mask = 0x3 << 20,
315 .main_output_mask = 0x1,
323 gpu_pll_config.l = 0x29;
324 gpu_pll_config.alpha_hi = 0xaa;
328 gpu_pll_config.l = 0x26;
329 gpu_pll_config.alpha_hi = 0x8a;