Lines Matching +full:0 +full:x1004
21 #define CX_GMU_CBCR_SLEEP_MASK 0xF
23 #define CX_GMU_CBCR_WAKE_MASK 0xF
34 { 249600000, 2000000000, 0 },
38 .offset = 0x100,
55 { P_BI_TCXO, 0 },
69 F(19200000, P_BI_TCXO, 1, 0, 0),
70 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
75 .cmd_rcgr = 0x1120,
76 .mnd_width = 0,
90 .halt_reg = 0x107c,
93 .enable_reg = 0x107c,
94 .enable_mask = BIT(0),
103 .halt_reg = 0x1098,
106 .enable_reg = 0x1098,
107 .enable_mask = BIT(0),
121 .halt_reg = 0x108c,
124 .enable_reg = 0x108c,
125 .enable_mask = BIT(0),
134 .halt_reg = 0x1004,
137 .enable_reg = 0x1004,
138 .enable_mask = BIT(0),
147 .halt_reg = 0x109c,
150 .enable_reg = 0x109c,
151 .enable_mask = BIT(0),
160 .gdscr = 0x106c,
161 .gds_hw_ctrl = 0x1540,
171 .gdscr = 0x100c,
172 .clamp_io_ctrl = 0x1508,
200 .max_register = 0x8008,
229 gpu_cc_pll_config.l = 0x12; in gpu_cc_sc7180_probe()
230 gpu_cc_pll_config.alpha = 0xc000; in gpu_cc_sc7180_probe()
231 gpu_cc_pll_config.config_ctl_val = 0x20485699; in gpu_cc_sc7180_probe()
232 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; in gpu_cc_sc7180_probe()
233 gpu_cc_pll_config.user_ctl_val = 0x00000001; in gpu_cc_sc7180_probe()
234 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; in gpu_cc_sc7180_probe()
235 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; in gpu_cc_sc7180_probe()
242 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; in gpu_cc_sc7180_probe()
243 regmap_update_bits(regmap, 0x1098, mask, value); in gpu_cc_sc7180_probe()