Lines Matching +full:0 +full:x10b0
35 .halt_reg = 0x1020,
37 .enable_reg = 0x1020,
38 .enable_mask = BIT(0),
52 { 249600000, 2000000000, 0 },
57 { 0x0, 1 },
58 { 0x1, 2 },
59 { 0x3, 4 },
60 { 0x7, 8 },
65 .offset = 0x0,
78 .offset = 0x0,
94 { P_XO, 0 },
104 { P_XO, 0 },
114 F(19200000, P_XO, 1, 0, 0),
115 F(50000000, P_GPLL0, 12, 0, 0),
120 .cmd_rcgr = 0x1030,
138 .cmd_rcgr = 0x1070,
152 F(19200000, P_XO, 1, 0, 0),
157 .cmd_rcgr = 0x10b0,
170 F(19200000, P_XO, 1, 0, 0),
171 F(40000000, P_GPLL0, 15, 0, 0),
172 F(200000000, P_GPLL0, 3, 0, 0),
173 F(300000000, P_GPLL0, 2, 0, 0),
178 .cmd_rcgr = 0x1100,
191 .halt_reg = 0x1054,
193 .enable_reg = 0x1054,
194 .enable_mask = BIT(0),
206 .halt_reg = 0x1098,
208 .enable_reg = 0x1098,
209 .enable_mask = BIT(0),
221 .halt_reg = 0x10d0,
223 .enable_reg = 0x10d0,
224 .enable_mask = BIT(0),
236 .halt_reg = 0x1124,
238 .enable_reg = 0x1124,
239 .enable_mask = BIT(0),
250 .gdscr = 0x1004,
251 .gds_hw_ctrl = 0x1008,
260 .gdscr = 0x1094,
261 .clamp_io_ctrl = 0x130,
264 .cxcs = (unsigned int []){ 0x1098 },
294 [GPU_CX_BCR] = { 0x1000 },
295 [RBCPR_BCR] = { 0x1050 },
296 [GPU_GX_BCR] = { 0x1090 },
297 [GPU_ISENSE_BCR] = { 0x1120 },
304 .max_register = 0x9000,
335 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); in gpucc_msm8998_probe()