Lines Matching +full:0 +full:x1020
34 .halt_reg = 0x1020,
36 .enable_reg = 0x1020,
37 .enable_mask = BIT(0),
51 { 249600000, 2000000000, 0 },
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
77 .offset = 0x0,
93 { P_XO, 0 },
103 { P_XO, 0 },
113 F(19200000, P_XO, 1, 0, 0),
114 F(50000000, P_GPLL0, 12, 0, 0),
119 .cmd_rcgr = 0x1030,
137 .cmd_rcgr = 0x1070,
151 F(19200000, P_XO, 1, 0, 0),
156 .cmd_rcgr = 0x10b0,
169 F(19200000, P_XO, 1, 0, 0),
170 F(40000000, P_GPLL0, 15, 0, 0),
171 F(200000000, P_GPLL0, 3, 0, 0),
172 F(300000000, P_GPLL0, 2, 0, 0),
177 .cmd_rcgr = 0x1100,
190 .halt_reg = 0x1054,
192 .enable_reg = 0x1054,
193 .enable_mask = BIT(0),
205 .halt_reg = 0x1098,
207 .enable_reg = 0x1098,
208 .enable_mask = BIT(0),
220 .halt_reg = 0x10d0,
222 .enable_reg = 0x10d0,
223 .enable_mask = BIT(0),
235 .halt_reg = 0x1124,
237 .enable_reg = 0x1124,
238 .enable_mask = BIT(0),
249 .gdscr = 0x1004,
250 .gds_hw_ctrl = 0x1008,
259 .gdscr = 0x1094,
260 .clamp_io_ctrl = 0x130,
263 .cxcs = (unsigned int []){ 0x1098 },
293 [GPU_CX_BCR] = { 0x1000 },
294 [RBCPR_BCR] = { 0x1050 },
295 [GPU_GX_BCR] = { 0x1090 },
296 [GPU_ISENSE_BCR] = { 0x1120 },
303 .max_register = 0x9000,
334 regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));