Lines Matching +full:0 +full:x28280
51 .offset = 0x0,
54 .enable_reg = 0x62018,
55 .enable_mask = BIT(0),
68 { 0x1, 2 }
72 .offset = 0x0,
89 .offset = 0x1000,
92 .enable_reg = 0x62018,
106 .offset = 0x1000,
123 .offset = 0x2000,
126 .enable_reg = 0x62018,
140 .offset = 0x2000,
157 .offset = 0x3000,
160 .enable_reg = 0x62018,
174 .offset = 0x4000,
177 .enable_reg = 0x62018,
191 .offset = 0x5000,
194 .enable_reg = 0x62018,
208 .offset = 0x5000,
225 .offset = 0x6000,
228 .enable_reg = 0x62018,
242 .offset = 0x7000,
245 .enable_reg = 0x62018,
259 .offset = 0x8000,
262 .enable_reg = 0x62018,
276 { P_BI_TCXO, 0 },
288 { P_BI_TCXO, 0 },
302 { P_BI_TCXO, 0 },
316 { P_BI_TCXO, 0 },
326 { P_BI_TCXO, 0 },
346 { P_BI_TCXO, 0 },
366 { P_PCIE_0_PHY_AUX_CLK, 0 },
376 { P_BI_TCXO, 0 },
392 { P_BI_TCXO, 0 },
410 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
420 .reg = 0x9d080,
421 .shift = 0,
435 .reg = 0x9d064,
449 .reg = 0x4906c,
450 .shift = 0,
464 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0),
465 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
470 .cmd_rcgr = 0x92020,
471 .mnd_width = 0,
484 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
485 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
490 .cmd_rcgr = 0x92038,
491 .mnd_width = 0,
504 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
509 .cmd_rcgr = 0x74004,
523 .cmd_rcgr = 0x75004,
537 .cmd_rcgr = 0x76004,
551 F(19200000, P_BI_TCXO, 1, 0, 0),
556 .cmd_rcgr = 0x9d068,
570 F(19200000, P_BI_TCXO, 1, 0, 0),
571 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
576 .cmd_rcgr = 0x9d04c,
577 .mnd_width = 0,
590 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
595 .cmd_rcgr = 0x43010,
596 .mnd_width = 0,
611 F(19200000, P_BI_TCXO, 1, 0, 0),
618 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
630 .cmd_rcgr = 0x27154,
646 .cmd_rcgr = 0x27288,
662 .cmd_rcgr = 0x273bc,
678 .cmd_rcgr = 0x274f0,
694 .cmd_rcgr = 0x27624,
703 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
715 .cmd_rcgr = 0x27758,
731 .cmd_rcgr = 0x2788c,
747 .cmd_rcgr = 0x279c0,
763 .cmd_rcgr = 0x28154,
779 .cmd_rcgr = 0x28288,
795 .cmd_rcgr = 0x283bc,
811 .cmd_rcgr = 0x284f0,
827 .cmd_rcgr = 0x28624,
843 .cmd_rcgr = 0x28758,
859 .cmd_rcgr = 0x2888c,
875 .cmd_rcgr = 0x289c0,
886 F(19200000, P_BI_TCXO, 1, 0, 0),
889 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
890 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
891 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
892 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
893 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
898 .cmd_rcgr = 0x3b034,
912 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
917 .cmd_rcgr = 0x3b01c,
918 .mnd_width = 0,
931 .cmd_rcgr = 0x5b00c,
932 .mnd_width = 0,
945 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
950 .cmd_rcgr = 0x57010,
951 .mnd_width = 0,
964 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
965 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
970 .cmd_rcgr = 0x49028,
984 .cmd_rcgr = 0x49044,
985 .mnd_width = 0,
998 .cmd_rcgr = 0x49070,
999 .mnd_width = 0,
1012 .reg = 0x4905c,
1013 .shift = 0,
1027 .halt_reg = 0x92008,
1029 .hwcg_reg = 0x92008,
1032 .enable_reg = 0x92008,
1033 .enable_mask = BIT(0),
1047 .halt_reg = 0x9201c,
1049 .hwcg_reg = 0x9201c,
1052 .enable_reg = 0x9201c,
1053 .enable_mask = BIT(0),
1067 .halt_reg = 0x48004,
1069 .hwcg_reg = 0x48004,
1072 .enable_reg = 0x62000,
1082 .halt_reg = 0x3e004,
1084 .hwcg_reg = 0x3e004,
1087 .enable_reg = 0x3e004,
1088 .enable_mask = BIT(0),
1097 .halt_reg = 0x8401c,
1099 .hwcg_reg = 0x8401c,
1102 .enable_reg = 0x8401c,
1103 .enable_mask = BIT(0),
1117 .halt_reg = 0x54030,
1119 .hwcg_reg = 0x54030,
1122 .enable_reg = 0x54030,
1123 .enable_mask = BIT(0),
1137 .halt_reg = 0x54298,
1139 .hwcg_reg = 0x54298,
1142 .enable_reg = 0x54298,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x3a008,
1159 .hwcg_reg = 0x3a008,
1162 .enable_reg = 0x3a008,
1163 .enable_mask = BIT(0),
1174 .enable_reg = 0x62010,
1175 .enable_mask = BIT(0),
1191 .enable_reg = 0x62010,
1208 .enable_reg = 0x62010,
1225 .enable_reg = 0x62010,
1242 .enable_reg = 0x62010,
1259 .enable_reg = 0x62010,
1274 .halt_reg = 0x3a004,
1277 .enable_reg = 0x3a004,
1278 .enable_mask = BIT(0),
1287 .halt_reg = 0x39010,
1290 .enable_reg = 0x39010,
1291 .enable_mask = BIT(0),
1300 .halt_reg = 0x39004,
1303 .enable_reg = 0x39004,
1304 .enable_mask = BIT(0),
1313 .halt_reg = 0x39008,
1316 .enable_reg = 0x39008,
1317 .enable_mask = BIT(0),
1326 .halt_reg = 0x3900c,
1329 .enable_reg = 0x3900c,
1330 .enable_mask = BIT(0),
1339 .halt_reg = 0x39014,
1342 .enable_reg = 0x39014,
1343 .enable_mask = BIT(0),
1352 .halt_reg = 0x3901c,
1354 .hwcg_reg = 0x3901c,
1357 .enable_reg = 0x3901c,
1358 .enable_mask = BIT(0),
1367 .halt_reg = 0x5402c,
1369 .hwcg_reg = 0x5402c,
1372 .enable_reg = 0x62008,
1373 .enable_mask = BIT(0),
1382 .halt_reg = 0x74000,
1385 .enable_reg = 0x74000,
1386 .enable_mask = BIT(0),
1400 .halt_reg = 0x75000,
1403 .enable_reg = 0x75000,
1404 .enable_mask = BIT(0),
1418 .halt_reg = 0x76000,
1421 .enable_reg = 0x76000,
1422 .enable_mask = BIT(0),
1436 .halt_reg = 0x9d030,
1438 .hwcg_reg = 0x9d030,
1441 .enable_reg = 0x62000,
1456 .halt_reg = 0x9d02c,
1458 .hwcg_reg = 0x9d02c,
1461 .enable_reg = 0x62000,
1471 .halt_reg = 0x9c004,
1474 .enable_reg = 0x9c004,
1475 .enable_mask = BIT(0),
1484 .halt_reg = 0x9d024,
1486 .hwcg_reg = 0x9d024,
1489 .enable_reg = 0x62000,
1499 .halt_reg = 0x9d038,
1501 .hwcg_reg = 0x9d038,
1504 .enable_reg = 0x62000,
1519 .halt_reg = 0x9d048,
1521 .hwcg_reg = 0x9d048,
1524 .enable_reg = 0x62000,
1539 .halt_reg = 0x9d040,
1541 .hwcg_reg = 0x9d040,
1544 .enable_reg = 0x62000,
1559 .halt_reg = 0x9d01c,
1561 .hwcg_reg = 0x9d01c,
1564 .enable_reg = 0x62000,
1574 .halt_reg = 0x9d018,
1576 .hwcg_reg = 0x9d018,
1579 .enable_reg = 0x62000,
1589 .halt_reg = 0x4300c,
1592 .enable_reg = 0x4300c,
1593 .enable_mask = BIT(0),
1607 .halt_reg = 0x43004,
1609 .hwcg_reg = 0x43004,
1612 .enable_reg = 0x43004,
1613 .enable_mask = BIT(0),
1622 .halt_reg = 0x43008,
1625 .enable_reg = 0x43008,
1626 .enable_mask = BIT(0),
1635 .halt_reg = 0x84044,
1637 .hwcg_reg = 0x84044,
1640 .enable_reg = 0x84044,
1641 .enable_mask = BIT(0),
1650 .halt_reg = 0x84038,
1652 .hwcg_reg = 0x84038,
1655 .enable_reg = 0x84038,
1656 .enable_mask = BIT(0),
1665 .halt_reg = 0x8403c,
1667 .hwcg_reg = 0x8403c,
1670 .enable_reg = 0x8403c,
1671 .enable_mask = BIT(0),
1680 .halt_reg = 0x84040,
1682 .hwcg_reg = 0x84040,
1685 .enable_reg = 0x84040,
1686 .enable_mask = BIT(0),
1695 .halt_reg = 0x27018,
1698 .enable_reg = 0x62008,
1708 .halt_reg = 0x2700c,
1711 .enable_reg = 0x62008,
1721 .halt_reg = 0x2714c,
1724 .enable_reg = 0x62008,
1739 .halt_reg = 0x27280,
1742 .enable_reg = 0x62008,
1757 .halt_reg = 0x273b4,
1760 .enable_reg = 0x62008,
1775 .halt_reg = 0x274e8,
1778 .enable_reg = 0x62008,
1793 .halt_reg = 0x2761c,
1796 .enable_reg = 0x62008,
1811 .halt_reg = 0x27750,
1814 .enable_reg = 0x62008,
1829 .halt_reg = 0x27884,
1832 .enable_reg = 0x62008,
1847 .halt_reg = 0x279b8,
1850 .enable_reg = 0x62008,
1865 .halt_reg = 0x28018,
1868 .enable_reg = 0x62008,
1878 .halt_reg = 0x2800c,
1881 .enable_reg = 0x62008,
1891 .halt_reg = 0x2814c,
1894 .enable_reg = 0x62008,
1909 .halt_reg = 0x28280,
1912 .enable_reg = 0x62008,
1927 .halt_reg = 0x283b4,
1930 .enable_reg = 0x62008,
1945 .halt_reg = 0x284e8,
1948 .enable_reg = 0x62008,
1963 .halt_reg = 0x2861c,
1966 .enable_reg = 0x62008,
1981 .halt_reg = 0x28750,
1984 .enable_reg = 0x62008,
1999 .halt_reg = 0x28884,
2002 .enable_reg = 0x62008,
2017 .halt_reg = 0x289b8,
2020 .enable_reg = 0x62008,
2035 .halt_reg = 0x27004,
2037 .hwcg_reg = 0x27004,
2040 .enable_reg = 0x62008,
2050 .halt_reg = 0x27008,
2052 .hwcg_reg = 0x27008,
2055 .enable_reg = 0x62008,
2065 .halt_reg = 0x28004,
2067 .hwcg_reg = 0x28004,
2070 .enable_reg = 0x62008,
2080 .halt_reg = 0x28008,
2082 .hwcg_reg = 0x28008,
2085 .enable_reg = 0x62008,
2095 .halt_reg = 0x3b00c,
2098 .enable_reg = 0x3b00c,
2099 .enable_mask = BIT(0),
2108 .halt_reg = 0x3b004,
2111 .enable_reg = 0x3b004,
2112 .enable_mask = BIT(0),
2126 .halt_reg = 0x3b010,
2129 .enable_reg = 0x3b010,
2130 .enable_mask = BIT(0),
2144 .halt_reg = 0x5b004,
2147 .enable_reg = 0x5b004,
2148 .enable_mask = BIT(0),
2157 .halt_reg = 0x5b008,
2160 .enable_reg = 0x5b008,
2161 .enable_mask = BIT(0),
2175 .halt_reg = 0x9200c,
2177 .hwcg_reg = 0x9200c,
2180 .enable_reg = 0x62000,
2190 .halt_reg = 0x92010,
2192 .hwcg_reg = 0x92010,
2195 .enable_reg = 0x62000,
2205 .halt_reg = 0x84030,
2208 .enable_reg = 0x84030,
2209 .enable_mask = BIT(0),
2218 .halt_reg = 0x92014,
2220 .hwcg_reg = 0x92014,
2223 .enable_reg = 0x62000,
2233 .halt_reg = 0x92018,
2235 .hwcg_reg = 0x92018,
2238 .enable_reg = 0x62000,
2248 .halt_reg = 0x5700c,
2251 .enable_reg = 0x5700c,
2252 .enable_mask = BIT(0),
2261 .halt_reg = 0x57004,
2264 .enable_reg = 0x57004,
2265 .enable_mask = BIT(0),
2279 .halt_reg = 0x57008,
2282 .enable_reg = 0x57008,
2283 .enable_mask = BIT(0),
2297 .halt_reg = 0x9c008,
2300 .enable_reg = 0x9c008,
2301 .enable_mask = BIT(0),
2310 .halt_reg = 0x49018,
2313 .enable_reg = 0x49018,
2314 .enable_mask = BIT(0),
2328 .halt_reg = 0x49024,
2331 .enable_reg = 0x49024,
2332 .enable_mask = BIT(0),
2346 .halt_reg = 0x49020,
2349 .enable_reg = 0x49020,
2350 .enable_mask = BIT(0),
2359 .halt_reg = 0x49060,
2362 .enable_reg = 0x49060,
2363 .enable_mask = BIT(0),
2377 .halt_reg = 0x49064,
2380 .enable_reg = 0x49064,
2381 .enable_mask = BIT(0),
2395 .halt_reg = 0x49068,
2397 .hwcg_reg = 0x49068,
2400 .enable_reg = 0x49068,
2401 .enable_mask = BIT(0),
2415 .gdscr = 0x9d004,
2416 .en_rest_wait_val = 0x2,
2417 .en_few_wait_val = 0x2,
2418 .clk_dis_wait_val = 0xf,
2426 .gdscr = 0x7c004,
2427 .en_rest_wait_val = 0x2,
2428 .en_few_wait_val = 0x2,
2429 .clk_dis_wait_val = 0x2,
2437 .gdscr = 0x49004,
2438 .en_rest_wait_val = 0x2,
2439 .en_few_wait_val = 0x2,
2440 .clk_dis_wait_val = 0xf,
2590 [GCC_ECPRI_CC_BCR] = { 0x3e000 },
2591 [GCC_ECPRI_SS_BCR] = { 0x3a000 },
2592 [GCC_ETH_WRAPPER_BCR] = { 0x39000 },
2593 [GCC_PCIE_0_BCR] = { 0x9d000 },
2594 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 },
2595 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 },
2596 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
2597 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
2598 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2599 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2600 [GCC_PDM_BCR] = { 0x43000 },
2601 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
2602 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
2603 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2604 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2605 [GCC_SDCC5_BCR] = { 0x3b000 },
2606 [GCC_TSC_BCR] = { 0x57000 },
2607 [GCC_USB30_PRIM_BCR] = { 0x49000 },
2608 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2609 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2610 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2611 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2612 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2613 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2614 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
2640 .max_register = 0x1f41f0,
2670 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14)); in gcc_qdu1000_probe()