Lines Matching +full:0 +full:x33000
53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
86 .n_reg = 0x2000c,
87 .config_reg = 0x20010,
88 .mode_reg = 0x20000,
89 .status_reg = 0x2001c,
102 .enable_reg = 0x45000,
115 .l_reg = 0x4a004,
116 .m_reg = 0x4a008,
117 .n_reg = 0x4a00c,
118 .config_reg = 0x4a010,
119 .mode_reg = 0x4a000,
120 .status_reg = 0x4a01c,
133 .enable_reg = 0x45000,
146 .l_reg = 0x23004,
147 .m_reg = 0x23008,
148 .n_reg = 0x2300c,
149 .config_reg = 0x23010,
150 .mode_reg = 0x23000,
151 .status_reg = 0x2301c,
164 .enable_reg = 0x45000,
177 .l_reg = 0x22004,
178 .m_reg = 0x22008,
179 .n_reg = 0x2200c,
180 .config_reg = 0x22010,
181 .mode_reg = 0x22000,
182 .status_reg = 0x2201c,
195 .enable_reg = 0x45000,
212 .vco_val = 0x0,
214 .pre_div_val = 0x0,
216 .post_div_val = 0x0,
219 .main_output_mask = BIT(0),
224 .l_reg = 0x24004,
225 .m_reg = 0x24008,
226 .n_reg = 0x2400c,
227 .config_reg = 0x24010,
228 .mode_reg = 0x24000,
229 .status_reg = 0x2401c,
242 .enable_reg = 0x45000,
259 .vco_val = 0x0,
261 .pre_div_val = 0x0,
263 .post_div_val = 0x0,
266 .main_output_mask = BIT(0),
270 .l_reg = 0x25004,
271 .m_reg = 0x25008,
272 .n_reg = 0x2500c,
273 .config_reg = 0x25010,
274 .mode_reg = 0x25000,
275 .status_reg = 0x2501c,
288 .enable_reg = 0x45000,
301 .l_reg = 0x37004,
302 .m_reg = 0x37008,
303 .n_reg = 0x3700c,
304 .config_reg = 0x37010,
305 .mode_reg = 0x37000,
306 .status_reg = 0x3701c,
319 .enable_reg = 0x45000,
332 { P_XO, 0 },
342 { P_XO, 0 },
354 { P_XO, 0 },
366 { P_XO, 0 },
382 { P_XO, 0 },
394 { P_XO, 0 },
408 { P_XO, 0 },
418 { P_XO, 0 },
432 { P_XO, 0 },
448 { P_XO, 0 },
460 { P_XO, 0, },
470 { P_XO, 0 },
482 { P_XO, 0 },
500 { P_XO, 0 },
512 { P_XO, 0 },
528 { P_XO, 0 },
542 { P_XO, 0 },
558 { P_XO, 0 },
574 { P_XO, 0 },
584 { P_XO, 0 },
610 .cmd_rcgr = 0x27000,
622 .cmd_rcgr = 0x26004,
634 .cmd_rcgr = 0x32024,
647 .cmd_rcgr = 0x2600c,
660 F(80000000, P_GPLL0, 10, 0, 0),
665 .cmd_rcgr = 0x5a000,
679 F(19200000, P_XO, 1, 0, 0),
680 F(50000000, P_GPLL0, 16, 0, 0),
681 F(100000000, P_GPLL0, 8, 0, 0),
682 F(133330000, P_GPLL0, 6, 0, 0),
687 .cmd_rcgr = 0x46000,
700 F(100000000, P_GPLL0, 8, 0, 0),
701 F(200000000, P_GPLL0, 4, 0, 0),
706 .cmd_rcgr = 0x4e020,
719 .cmd_rcgr = 0x4f020,
732 .cmd_rcgr = 0x3c020,
745 F(19200000, P_XO, 1, 0, 0),
746 F(50000000, P_GPLL0, 16, 0, 0),
747 F(80000000, P_GPLL0, 10, 0, 0),
748 F(100000000, P_GPLL0, 8, 0, 0),
749 F(160000000, P_GPLL0, 5, 0, 0),
750 F(200000000, P_GPLL0, 4, 0, 0),
751 F(220000000, P_GPLL3, 5, 0, 0),
752 F(266670000, P_GPLL0, 3, 0, 0),
753 F(310000000, P_GPLL2_AUX, 3, 0, 0),
754 F(400000000, P_GPLL0, 2, 0, 0),
755 F(465000000, P_GPLL2_AUX, 2, 0, 0),
756 F(550000000, P_GPLL3, 2, 0, 0),
761 .cmd_rcgr = 0x59000,
774 F(50000000, P_GPLL0, 16, 0, 0),
775 F(80000000, P_GPLL0, 10, 0, 0),
776 F(100000000, P_GPLL0, 8, 0, 0),
777 F(160000000, P_GPLL0, 5, 0, 0),
778 F(177780000, P_GPLL0, 4.5, 0, 0),
779 F(200000000, P_GPLL0, 4, 0, 0),
780 F(266670000, P_GPLL0, 3, 0, 0),
781 F(320000000, P_GPLL0, 2.5, 0, 0),
782 F(400000000, P_GPLL0, 2, 0, 0),
783 F(465000000, P_GPLL2, 2, 0, 0),
784 F(480000000, P_GPLL4, 2.5, 0, 0),
785 F(600000000, P_GPLL4, 2, 0, 0),
790 .cmd_rcgr = 0x58000,
803 F(19200000, P_XO, 1, 0, 0),
804 F(50000000, P_GPLL0, 16, 0, 0),
809 .cmd_rcgr = 0x0200c,
823 F(4800000, P_XO, 4, 0, 0),
824 F(9600000, P_XO, 2, 0, 0),
826 F(19200000, P_XO, 1, 0, 0),
828 F(50000000, P_GPLL0, 16, 0, 0),
833 .cmd_rcgr = 0x02024,
847 .cmd_rcgr = 0x03000,
860 .cmd_rcgr = 0x03014,
874 .cmd_rcgr = 0x04000,
887 .cmd_rcgr = 0x04024,
901 .cmd_rcgr = 0x05000,
914 .cmd_rcgr = 0x05024,
928 .cmd_rcgr = 0x06000,
941 .cmd_rcgr = 0x06024,
955 .cmd_rcgr = 0x07000,
968 .cmd_rcgr = 0x07024,
986 F(19200000, P_XO, 1, 0, 0),
1001 .cmd_rcgr = 0x02044,
1015 .cmd_rcgr = 0x03034,
1029 F(19200000, P_XO, 1, 0, 0),
1035 .cmd_rcgr = 0x51000,
1062 F(100000000, P_GPLL0, 8, 0, 0),
1063 F(200000000, P_GPLL0, 4, 0, 0),
1068 .cmd_rcgr = 0x54000,
1082 .cmd_rcgr = 0x55000,
1096 F(133330000, P_GPLL0, 6, 0, 0),
1097 F(266670000, P_GPLL0, 3, 0, 0),
1098 F(320000000, P_GPLL0, 2.5, 0, 0),
1103 .cmd_rcgr = 0x57000,
1117 F(66670000, P_GPLL0, 12, 0, 0),
1122 .cmd_rcgr = 0x52000,
1136 .cmd_rcgr = 0x53000,
1150 F(100000000, P_GPLL0, 8, 0, 0),
1151 F(200000000, P_GPLL0, 4, 0, 0),
1156 .cmd_rcgr = 0x4e000,
1169 .cmd_rcgr = 0x4f000,
1182 F(160000000, P_GPLL0, 5, 0, 0),
1183 F(200000000, P_GPLL0, 4, 0, 0),
1184 F(228570000, P_GPLL0, 3.5, 0, 0),
1185 F(266670000, P_GPLL0, 3, 0, 0),
1186 F(320000000, P_GPLL0, 2.5, 0, 0),
1187 F(465000000, P_GPLL2, 2, 0, 0),
1192 .cmd_rcgr = 0x58018,
1205 F(50000000, P_GPLL0, 16, 0, 0),
1206 F(80000000, P_GPLL0, 10, 0, 0),
1207 F(100000000, P_GPLL0, 8, 0, 0),
1208 F(160000000, P_GPLL0, 5, 0, 0),
1214 .cmd_rcgr = 0x16004,
1249 F(19200000, P_XO, 1, 0, 0),
1254 .cmd_rcgr = 0x08004,
1268 .cmd_rcgr = 0x09004,
1282 .cmd_rcgr = 0x0a004,
1296 .cmd_rcgr = 0x4d044,
1309 .cmd_rcgr = 0x4d0b0,
1322 F(19200000, P_XO, 1, 0, 0),
1327 .cmd_rcgr = 0x4d060,
1340 .cmd_rcgr = 0x4d0a8,
1353 F(50000000, P_GPLL0_AUX, 16, 0, 0),
1354 F(80000000, P_GPLL0_AUX, 10, 0, 0),
1355 F(100000000, P_GPLL0_AUX, 8, 0, 0),
1356 F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1357 F(153600000, P_GPLL0, 4, 0, 0),
1358 F(160000000, P_GPLL0_AUX, 5, 0, 0),
1359 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1360 F(200000000, P_GPLL0_AUX, 4, 0, 0),
1361 F(266670000, P_GPLL0_AUX, 3, 0, 0),
1362 F(307200000, P_GPLL1, 2, 0, 0),
1363 F(366670000, P_GPLL3_AUX, 3, 0, 0),
1368 .cmd_rcgr = 0x4d014,
1381 .cmd_rcgr = 0x4d000,
1395 .cmd_rcgr = 0x4d0b8,
1409 F(19200000, P_XO, 1, 0, 0),
1414 .cmd_rcgr = 0x4d02c,
1427 F(64000000, P_GPLL0, 12.5, 0, 0),
1433 .cmd_rcgr = 0x44010,
1450 F(50000000, P_GPLL0, 16, 0, 0),
1451 F(100000000, P_GPLL0, 8, 0, 0),
1452 F(177770000, P_GPLL0, 4.5, 0, 0),
1453 F(200000000, P_GPLL0, 4, 0, 0),
1458 .cmd_rcgr = 0x42004,
1472 .cmd_rcgr = 0x43004,
1486 F(154285000, P_GPLL6, 7, 0, 0),
1487 F(320000000, P_GPLL0, 2.5, 0, 0),
1488 F(400000000, P_GPLL0, 2, 0, 0),
1493 .cmd_rcgr = 0x1207c,
1506 F(19200000, P_XO, 1, 0, 0),
1507 F(100000000, P_GPLL0, 8, 0, 0),
1508 F(200000000, P_GPLL0, 4, 0, 0),
1509 F(266500000, P_BIMC, 4, 0, 0),
1510 F(400000000, P_GPLL0, 2, 0, 0),
1511 F(533000000, P_BIMC, 2, 0, 0),
1516 .cmd_rcgr = 0x31028,
1530 F(57140000, P_GPLL0, 14, 0, 0),
1531 F(80000000, P_GPLL0, 10, 0, 0),
1532 F(100000000, P_GPLL0, 8, 0, 0),
1537 .cmd_rcgr = 0x41010,
1550 F(64000000, P_GPLL0, 12.5, 0, 0),
1555 .cmd_rcgr = 0x3f010,
1573 .cmd_rcgr = 0x3f034,
1586 F(3200000, P_XO, 6, 0, 0),
1587 F(6400000, P_XO, 3, 0, 0),
1588 F(9600000, P_XO, 2, 0, 0),
1589 F(19200000, P_XO, 1, 0, 0),
1591 F(66670000, P_GPLL0, 12, 0, 0),
1592 F(80000000, P_GPLL0, 10, 0, 0),
1593 F(100000000, P_GPLL0, 8, 0, 0),
1598 .cmd_rcgr = 0x1c010,
1612 .halt_reg = 0x1c028,
1614 .enable_reg = 0x1c028,
1615 .enable_mask = BIT(0),
1629 .halt_reg = 0x1c024,
1631 .enable_reg = 0x1c024,
1632 .enable_mask = BIT(0),
1658 F(1600000, P_XO, 12, 0, 0),
1662 F(2400000, P_XO, 8, 0, 0),
1666 F(4800000, P_XO, 4, 0, 0),
1670 F(9600000, P_XO, 2, 0, 0),
1677 .cmd_rcgr = 0x1c054,
1691 .halt_reg = 0x1c068,
1693 .enable_reg = 0x1c068,
1694 .enable_mask = BIT(0),
1708 .cmd_rcgr = 0x1c06c,
1722 .halt_reg = 0x1c080,
1724 .enable_reg = 0x1c080,
1725 .enable_mask = BIT(0),
1739 .cmd_rcgr = 0x1c084,
1753 .halt_reg = 0x1c098,
1755 .enable_reg = 0x1c098,
1756 .enable_mask = BIT(0),
1770 F(19200000, P_XO, 1, 0, 0),
1775 .cmd_rcgr = 0x1c034,
1788 .halt_reg = 0x1c04c,
1790 .enable_reg = 0x1c04c,
1791 .enable_mask = BIT(0),
1805 .halt_reg = 0x1c050,
1807 .enable_reg = 0x1c050,
1808 .enable_mask = BIT(0),
1822 F(9600000, P_XO, 2, 0, 0),
1824 F(19200000, P_XO, 1, 0, 0),
1825 F(11289600, P_EXT_MCLK, 1, 0, 0),
1830 .cmd_rcgr = 0x1c09c,
1844 .halt_reg = 0x1c0b0,
1846 .enable_reg = 0x1c0b0,
1847 .enable_mask = BIT(0),
1861 .halt_reg = 0x1c000,
1863 .enable_reg = 0x1c000,
1864 .enable_mask = BIT(0),
1877 .halt_reg = 0x1c004,
1879 .enable_reg = 0x1c004,
1880 .enable_mask = BIT(0),
1893 F(133330000, P_GPLL0, 6, 0, 0),
1894 F(200000000, P_GPLL0, 4, 0, 0),
1895 F(266670000, P_GPLL0, 3, 0, 0),
1900 .cmd_rcgr = 0x4C000,
1914 .halt_reg = 0x01008,
1917 .enable_reg = 0x45004,
1931 .halt_reg = 0x01004,
1933 .enable_reg = 0x01004,
1934 .enable_mask = BIT(0),
1943 .halt_reg = 0x02008,
1945 .enable_reg = 0x02008,
1946 .enable_mask = BIT(0),
1960 .halt_reg = 0x02004,
1962 .enable_reg = 0x02004,
1963 .enable_mask = BIT(0),
1977 .halt_reg = 0x03010,
1979 .enable_reg = 0x03010,
1980 .enable_mask = BIT(0),
1994 .halt_reg = 0x0300c,
1996 .enable_reg = 0x0300c,
1997 .enable_mask = BIT(0),
2011 .halt_reg = 0x04020,
2013 .enable_reg = 0x04020,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0x0401c,
2030 .enable_reg = 0x0401c,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x05020,
2047 .enable_reg = 0x05020,
2048 .enable_mask = BIT(0),
2062 .halt_reg = 0x0501c,
2064 .enable_reg = 0x0501c,
2065 .enable_mask = BIT(0),
2079 .halt_reg = 0x06020,
2081 .enable_reg = 0x06020,
2082 .enable_mask = BIT(0),
2096 .halt_reg = 0x0601c,
2098 .enable_reg = 0x0601c,
2099 .enable_mask = BIT(0),
2113 .halt_reg = 0x07020,
2115 .enable_reg = 0x07020,
2116 .enable_mask = BIT(0),
2130 .halt_reg = 0x0701c,
2132 .enable_reg = 0x0701c,
2133 .enable_mask = BIT(0),
2147 .halt_reg = 0x0203c,
2149 .enable_reg = 0x0203c,
2150 .enable_mask = BIT(0),
2164 .halt_reg = 0x0302c,
2166 .enable_reg = 0x0302c,
2167 .enable_mask = BIT(0),
2181 .halt_reg = 0x1300c,
2184 .enable_reg = 0x45004,
2198 .halt_reg = 0x5101c,
2200 .enable_reg = 0x5101c,
2201 .enable_mask = BIT(0),
2215 .halt_reg = 0x51018,
2217 .enable_reg = 0x51018,
2218 .enable_mask = BIT(0),
2232 .halt_reg = 0x4e040,
2234 .enable_reg = 0x4e040,
2235 .enable_mask = BIT(0),
2249 .halt_reg = 0x4e03c,
2251 .enable_reg = 0x4e03c,
2252 .enable_mask = BIT(0),
2266 .halt_reg = 0x4e048,
2268 .enable_reg = 0x4e048,
2269 .enable_mask = BIT(0),
2283 .halt_reg = 0x4e058,
2285 .enable_reg = 0x4e058,
2286 .enable_mask = BIT(0),
2300 .halt_reg = 0x4e050,
2302 .enable_reg = 0x4e050,
2303 .enable_mask = BIT(0),
2317 .halt_reg = 0x4f040,
2319 .enable_reg = 0x4f040,
2320 .enable_mask = BIT(0),
2334 .halt_reg = 0x4f03c,
2336 .enable_reg = 0x4f03c,
2337 .enable_mask = BIT(0),
2351 .halt_reg = 0x4f048,
2353 .enable_reg = 0x4f048,
2354 .enable_mask = BIT(0),
2368 .halt_reg = 0x4f058,
2370 .enable_reg = 0x4f058,
2371 .enable_mask = BIT(0),
2385 .halt_reg = 0x4f050,
2387 .enable_reg = 0x4f050,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0x3c040,
2404 .enable_reg = 0x3c040,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x3c03c,
2421 .enable_reg = 0x3c03c,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x3c048,
2438 .enable_reg = 0x3c048,
2439 .enable_mask = BIT(0),
2453 .halt_reg = 0x3c058,
2455 .enable_reg = 0x3c058,
2456 .enable_mask = BIT(0),
2470 .halt_reg = 0x3c050,
2472 .enable_reg = 0x3c050,
2473 .enable_mask = BIT(0),
2487 .halt_reg = 0x58050,
2489 .enable_reg = 0x58050,
2490 .enable_mask = BIT(0),
2504 .halt_reg = 0x54018,
2506 .enable_reg = 0x54018,
2507 .enable_mask = BIT(0),
2521 .halt_reg = 0x55018,
2523 .enable_reg = 0x55018,
2524 .enable_mask = BIT(0),
2538 .halt_reg = 0x50004,
2540 .enable_reg = 0x50004,
2541 .enable_mask = BIT(0),
2555 .halt_reg = 0x57020,
2557 .enable_reg = 0x57020,
2558 .enable_mask = BIT(0),
2572 .halt_reg = 0x57024,
2574 .enable_reg = 0x57024,
2575 .enable_mask = BIT(0),
2589 .halt_reg = 0x57028,
2591 .enable_reg = 0x57028,
2592 .enable_mask = BIT(0),
2606 .halt_reg = 0x52018,
2608 .enable_reg = 0x52018,
2609 .enable_mask = BIT(0),
2623 .halt_reg = 0x53018,
2625 .enable_reg = 0x53018,
2626 .enable_mask = BIT(0),
2640 .halt_reg = 0x5600c,
2642 .enable_reg = 0x5600c,
2643 .enable_mask = BIT(0),
2657 .halt_reg = 0x4e01c,
2659 .enable_reg = 0x4e01c,
2660 .enable_mask = BIT(0),
2674 .halt_reg = 0x4f01c,
2676 .enable_reg = 0x4f01c,
2677 .enable_mask = BIT(0),
2691 .halt_reg = 0x5a014,
2693 .enable_reg = 0x5a014,
2694 .enable_mask = BIT(0),
2708 .halt_reg = 0x56004,
2710 .enable_reg = 0x56004,
2711 .enable_mask = BIT(0),
2725 .halt_reg = 0x58040,
2727 .enable_reg = 0x58040,
2728 .enable_mask = BIT(0),
2742 .halt_reg = 0x5803c,
2744 .enable_reg = 0x5803c,
2745 .enable_mask = BIT(0),
2759 .halt_reg = 0x58038,
2761 .enable_reg = 0x58038,
2762 .enable_mask = BIT(0),
2776 .halt_reg = 0x58044,
2778 .enable_reg = 0x58044,
2779 .enable_mask = BIT(0),
2793 .halt_reg = 0x58048,
2795 .enable_reg = 0x58048,
2796 .enable_mask = BIT(0),
2810 .halt_reg = 0x16024,
2813 .enable_reg = 0x45004,
2814 .enable_mask = BIT(0),
2828 .halt_reg = 0x16020,
2831 .enable_reg = 0x45004,
2846 .halt_reg = 0x1601c,
2849 .enable_reg = 0x45004,
2864 .halt_reg = 0x59024,
2866 .enable_reg = 0x59024,
2867 .enable_mask = BIT(0),
2881 .halt_reg = 0x08000,
2883 .enable_reg = 0x08000,
2884 .enable_mask = BIT(0),
2898 .halt_reg = 0x09000,
2900 .enable_reg = 0x09000,
2901 .enable_mask = BIT(0),
2915 .halt_reg = 0x0a000,
2917 .enable_reg = 0x0a000,
2918 .enable_mask = BIT(0),
2932 .halt_reg = 0x4d07c,
2934 .enable_reg = 0x4d07c,
2935 .enable_mask = BIT(0),
2949 .halt_reg = 0x4d080,
2951 .enable_reg = 0x4d080,
2952 .enable_mask = BIT(0),
2966 .halt_reg = 0x4d094,
2968 .enable_reg = 0x4d094,
2969 .enable_mask = BIT(0),
2983 .halt_reg = 0x4d0a0,
2985 .enable_reg = 0x4d0a0,
2986 .enable_mask = BIT(0),
3000 .halt_reg = 0x4d098,
3002 .enable_reg = 0x4d098,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x4d09c,
3019 .enable_reg = 0x4d09c,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x4D088,
3036 .enable_reg = 0x4D088,
3037 .enable_mask = BIT(0),
3051 .halt_reg = 0x4d084,
3053 .enable_reg = 0x4d084,
3054 .enable_mask = BIT(0),
3068 .halt_reg = 0x4d0a4,
3070 .enable_reg = 0x4d0a4,
3071 .enable_mask = BIT(0),
3085 .halt_reg = 0x4d090,
3087 .enable_reg = 0x4d090,
3088 .enable_mask = BIT(0),
3102 .halt_reg = 0x49000,
3104 .enable_reg = 0x49000,
3105 .enable_mask = BIT(0),
3119 .halt_reg = 0x49004,
3121 .enable_reg = 0x49004,
3122 .enable_mask = BIT(0),
3136 .halt_reg = 0x59028,
3138 .enable_reg = 0x59028,
3139 .enable_mask = BIT(0),
3153 .halt_reg = 0x59020,
3155 .enable_reg = 0x59020,
3156 .enable_mask = BIT(0),
3170 .halt_reg = 0x4400c,
3172 .enable_reg = 0x4400c,
3173 .enable_mask = BIT(0),
3187 .halt_reg = 0x44004,
3189 .enable_reg = 0x44004,
3190 .enable_mask = BIT(0),
3204 .halt_reg = 0x13004,
3207 .enable_reg = 0x45004,
3221 .halt_reg = 0x4201c,
3223 .enable_reg = 0x4201c,
3224 .enable_mask = BIT(0),
3238 .halt_reg = 0x42018,
3240 .enable_reg = 0x42018,
3241 .enable_mask = BIT(0),
3255 .halt_reg = 0x4301c,
3257 .enable_reg = 0x4301c,
3258 .enable_mask = BIT(0),
3272 .halt_reg = 0x43018,
3274 .enable_reg = 0x43018,
3275 .enable_mask = BIT(0),
3289 .halt_reg = 0x12018,
3292 .enable_reg = 0x4500c,
3306 .halt_reg = 0x12020,
3309 .enable_reg = 0x4500c,
3323 .halt_reg = 0x12010,
3326 .enable_reg = 0x4500c,
3340 .halt_reg = 0x1201c,
3343 .enable_reg = 0x4500c,
3358 .halt_reg = 0x12014,
3361 .enable_reg = 0x4500c,
3376 .halt_reg = 0x1203c,
3379 .enable_reg = 0x4500c,
3394 .halt_reg = 0x12034,
3397 .enable_reg = 0x4500c,
3412 .halt_reg = 0x12038,
3415 .enable_reg = 0x4500c,
3430 .halt_reg = 0x12044,
3433 .enable_reg = 0x4500c,
3448 .halt_reg = 0x12040,
3451 .enable_reg = 0x4500c,
3466 .halt_reg = 0x1201c,
3469 .enable_reg = 0x4500c,
3484 .halt_reg = 0x31024,
3486 .enable_reg = 0x31024,
3487 .enable_mask = BIT(0),
3501 .halt_reg = 0x31040,
3503 .enable_reg = 0x31040,
3504 .enable_mask = BIT(0),
3518 .halt_reg = 0x4102c,
3520 .enable_reg = 0x4102c,
3521 .enable_mask = BIT(0),
3530 .halt_reg = 0x3f008,
3532 .enable_reg = 0x3f008,
3533 .enable_mask = BIT(0),
3547 .halt_reg = 0x3f030,
3549 .enable_reg = 0x3f030,
3550 .enable_mask = BIT(0),
3564 .halt_reg = 0x3f004,
3566 .enable_reg = 0x3f004,
3567 .enable_mask = BIT(0),
3581 .halt_reg = 0x41008,
3583 .enable_reg = 0x41008,
3584 .enable_mask = BIT(0),
3598 .halt_reg = 0x41004,
3600 .enable_reg = 0x41004,
3601 .enable_mask = BIT(0),
3615 .halt_reg = 0x4c020,
3617 .enable_reg = 0x4c020,
3618 .enable_mask = BIT(0),
3632 .halt_reg = 0x4c024,
3634 .enable_reg = 0x4c024,
3635 .enable_mask = BIT(0),
3649 .halt_reg = 0x4c01c,
3651 .enable_reg = 0x4c01c,
3652 .enable_mask = BIT(0),
3666 .halt_reg = 0x4c02c,
3668 .enable_reg = 0x4c02c,
3669 .enable_mask = BIT(0),
3683 .halt_reg = 0x4c034,
3685 .enable_reg = 0x4c034,
3686 .enable_mask = BIT(0),
3700 .halt_reg = 0x59040,
3702 .enable_reg = 0x59040,
3703 .enable_mask = BIT(0),
3712 .gdscr = 0x4c018,
3720 .gdscr = 0x4d078,
3728 .gdscr = 0x5701c,
3736 .gdscr = 0x58034,
3744 .gdscr = 0x5901c,
3752 .gdscr = 0x4c028,
3760 .gdscr = 0x4c030,
3974 [GCC_BLSP1_BCR] = { 0x01000 },
3975 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3976 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3977 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3978 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3979 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3980 [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3981 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3982 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3983 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3984 [GCC_IMEM_BCR] = { 0x0e000 },
3985 [GCC_SMMU_BCR] = { 0x12000 },
3986 [GCC_APSS_TCU_BCR] = { 0x12050 },
3987 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3988 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3989 [GCC_PRNG_BCR] = { 0x13000 },
3990 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3991 [GCC_CRYPTO_BCR] = { 0x16000 },
3992 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3993 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3994 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3995 [GCC_DEHR_BCR] = { 0x1f000 },
3996 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3997 [GCC_PCNOC_BCR] = { 0x27018 },
3998 [GCC_TCSR_BCR] = { 0x28000 },
3999 [GCC_QDSS_BCR] = { 0x29000 },
4000 [GCC_DCD_BCR] = { 0x2a000 },
4001 [GCC_MSG_RAM_BCR] = { 0x2b000 },
4002 [GCC_MPM_BCR] = { 0x2c000 },
4003 [GCC_SPMI_BCR] = { 0x2e000 },
4004 [GCC_SPDM_BCR] = { 0x2f000 },
4005 [GCC_MM_SPDM_BCR] = { 0x2f024 },
4006 [GCC_BIMC_BCR] = { 0x31000 },
4007 [GCC_RBCPR_BCR] = { 0x33000 },
4008 [GCC_TLMM_BCR] = { 0x34000 },
4009 [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
4010 [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
4011 [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
4012 [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
4013 [GCC_USB_FS_BCR] = { 0x3f000 },
4014 [GCC_USB_HS_BCR] = { 0x41000 },
4015 [GCC_USB2A_PHY_BCR] = { 0x41028 },
4016 [GCC_SDCC1_BCR] = { 0x42000 },
4017 [GCC_SDCC2_BCR] = { 0x43000 },
4018 [GCC_PDM_BCR] = { 0x44000 },
4019 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
4020 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
4021 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
4022 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
4023 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
4024 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
4025 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
4026 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
4027 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
4028 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
4029 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
4030 [GCC_MMSS_BCR] = { 0x4b000 },
4031 [GCC_VENUS0_BCR] = { 0x4c014 },
4032 [GCC_MDSS_BCR] = { 0x4d074 },
4033 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
4034 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
4035 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
4036 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
4037 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
4038 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
4039 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
4040 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
4041 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
4042 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
4043 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
4044 [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
4045 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
4046 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
4047 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
4048 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
4049 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
4050 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
4051 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
4052 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
4053 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
4054 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
4055 [GCC_OXILI_BCR] = { 0x59018 },
4056 [GCC_GMEM_BCR] = { 0x5902c },
4057 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
4058 [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
4059 [GCC_MDP_TBU_BCR] = { 0x62000 },
4060 [GCC_GFX_TBU_BCR] = { 0x63000 },
4061 [GCC_GFX_TCU_BCR] = { 0x64000 },
4062 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
4063 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
4064 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
4065 [GCC_GTCU_AHB_BCR] = { 0x68000 },
4066 [GCC_SMMU_CFG_BCR] = { 0x69000 },
4067 [GCC_VFE_TBU_BCR] = { 0x6a000 },
4068 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
4069 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
4070 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
4071 [GCC_CPP_TBU_BCR] = { 0x6e000 },
4072 [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
4073 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
4080 .max_register = 0x80000,