Lines Matching +full:0 +full:x37000
58 .offset = 0x21000,
61 .enable_reg = 0x45008,
76 .offset = 0x21000,
79 .enable_reg = 0x45000,
80 .enable_mask = BIT(0),
93 .offset = 0x21000,
106 { 700000000, 1400000000, 0 },
110 { 525000000, 1066000000, 0 },
115 .config_ctl_val = 0x4001055b,
116 .early_output_mask = 0,
122 .offset = 0x22000,
140 .offset = 0x22000,
154 .offset = 0x24000,
157 .enable_reg = 0x45000,
171 .offset = 0x24000,
184 .l_reg = 0x37004,
185 .m_reg = 0x37008,
186 .n_reg = 0x3700c,
187 .config_reg = 0x37014,
188 .mode_reg = 0x37000,
189 .status_reg = 0x3701c,
202 .enable_reg = 0x45000,
215 { P_XO, 0 },
220 { P_XO, 0 },
230 { P_XO, 0 },
244 { P_XO, 0 },
258 F(19200000, P_XO, 1, 0, 0),
259 F(50000000, P_GPLL0, 16, 0, 0),
260 F(100000000, P_GPLL0, 8, 0, 0),
261 F(133330000, P_GPLL0, 6, 0, 0),
266 .cmd_rcgr = 0x46000,
279 F(19200000, P_XO, 1, 0, 0),
280 F(50000000, P_GPLL0, 16, 0, 0),
285 .cmd_rcgr = 0x0200c,
298 .cmd_rcgr = 0x03000,
311 .cmd_rcgr = 0x04000,
324 .cmd_rcgr = 0x05000,
337 .cmd_rcgr = 0x0c00c,
350 .cmd_rcgr = 0x0d000,
363 .cmd_rcgr = 0x0f000,
376 .cmd_rcgr = 0x18000,
390 F(4800000, P_XO, 4, 0, 0),
391 F(9600000, P_XO, 2, 0, 0),
393 F(19200000, P_XO, 1, 0, 0),
395 F(50000000, P_GPLL0, 16, 0, 0),
400 .cmd_rcgr = 0x02024,
414 .cmd_rcgr = 0x03014,
428 .cmd_rcgr = 0x04024,
442 .cmd_rcgr = 0x05024,
456 .cmd_rcgr = 0x0c024,
470 .cmd_rcgr = 0x0d014,
484 .cmd_rcgr = 0x0f024,
498 .cmd_rcgr = 0x18024,
516 F(19200000, P_XO, 1, 0, 0),
532 .cmd_rcgr = 0x02044,
546 .cmd_rcgr = 0x03034,
560 .cmd_rcgr = 0x0c044,
574 .cmd_rcgr = 0x0d034,
588 { P_XO, 0 },
594 { P_XO, 0 },
606 .cmd_rcgr = 0x4d044,
619 .cmd_rcgr = 0x4d0b0,
632 F(100000000, P_GPLL0, 8, 0, 0),
633 F(160000000, P_GPLL0, 5, 0, 0),
634 F(200000000, P_GPLL0, 4, 0, 0),
639 .cmd_rcgr = 0x54000,
653 .cmd_rcgr = 0x55000,
668 F(61540000, P_GPLL0, 13, 0, 0),
669 F(80000000, P_GPLL0, 10, 0, 0),
674 .cmd_rcgr = 0x5a000,
687 F(19200000, P_XO, 1, 0, 0),
693 .cmd_rcgr = 0x51000,
707 { P_XO, 0 },
719 F(133330000, P_GPLL0, 6, 0, 0),
720 F(160000000, P_GPLL0, 5, 0, 0),
721 F(266670000, P_GPLL0, 3, 0, 0),
722 F(308570000, P_GPLL0, 3.5, 0, 0),
723 F(320000000, P_GPLL0, 2.5, 0, 0),
724 F(360000000, P_GPLL6, 3, 0, 0),
729 F(133330000, P_GPLL0, 6, 0, 0),
730 F(160000000, P_GPLL0, 5, 0, 0),
731 F(200000000, P_GPLL0, 5, 0, 0),
732 F(266666667, P_GPLL0, 3, 0, 0),
733 F(308570000, P_GPLL6, 3.5, 0, 0),
734 F(320000000, P_GPLL0, 2.5, 0, 0),
735 F(360000000, P_GPLL6, 3, 0, 0),
740 .cmd_rcgr = 0x58018,
760 F(50000000, P_GPLL0, 16, 0, 0),
761 F(80000000, P_GPLL0, 10, 0, 0),
762 F(100000000, P_GPLL0, 8, 0, 0),
763 F(160000000, P_GPLL0, 5, 0, 0),
768 .cmd_rcgr = 0x16004,
781 F(100000000, P_GPLL0, 8, 0, 0),
782 F(160000000, P_GPLL0, 5, 0, 0),
783 F(200000000, P_GPLL0, 4, 0, 0),
788 .cmd_rcgr = 0x4e020,
801 .cmd_rcgr = 0x4f020,
814 .cmd_rcgr = 0x3c020,
827 F(100000000, P_GPLL0, 8, 0, 0),
828 F(160000000, P_GPLL0, 5, 0, 0),
829 F(200000000, P_GPLL0, 4, 0, 0),
830 F(266670000, P_GPLL0, 3, 0, 0),
835 F(100000000, P_GPLL0, 8, 0, 0),
836 F(160000000, P_GPLL0, 5, 0, 0),
837 F(200000000, P_GPLL0, 4, 0, 0),
842 .cmd_rcgr = 0x4e000,
855 .cmd_rcgr = 0x4f000,
868 F(19200000, P_XO, 1, 0, 0),
873 .cmd_rcgr = 0x4d05c,
886 .cmd_rcgr = 0x4d0a8,
899 { P_XO, 0 },
906 { P_XO, 0 },
920 F(19200000, P_XO, 1, 0, 0),
921 F(50000000, P_GPLL0, 16, 0, 0),
922 F(80000000, P_GPLL0, 10, 0, 0),
923 F(100000000, P_GPLL0, 8, 0, 0),
924 F(160000000, P_GPLL0, 5, 0, 0),
925 F(200000000, P_GPLL0, 4, 0, 0),
926 F(228570000, P_GPLL0, 3.5, 0, 0),
927 F(240000000, P_GPLL6, 4.5, 0, 0),
928 F(266670000, P_GPLL0, 3, 0, 0),
929 F(270000000, P_GPLL6, 4, 0, 0),
930 F(320000000, P_GPLL0, 2.5, 0, 0),
931 F(400000000, P_GPLL0, 2, 0, 0),
932 F(465000000, P_GPLL3, 1, 0, 0),
933 F(484800000, P_GPLL3, 1, 0, 0),
934 F(500000000, P_GPLL3, 1, 0, 0),
935 F(523200000, P_GPLL3, 1, 0, 0),
936 F(550000000, P_GPLL3, 1, 0, 0),
937 F(598000000, P_GPLL3, 1, 0, 0),
942 F(19200000, P_XO, 1, 0, 0),
943 F(50000000, P_GPLL0, 16, 0, 0),
944 F(80000000, P_GPLL0, 10, 0, 0),
945 F(100000000, P_GPLL0, 8, 0, 0),
946 F(160000000, P_GPLL0, 5, 0, 0),
947 F(200000000, P_GPLL0, 4, 0, 0),
948 F(216000000, P_GPLL6, 5, 0, 0),
949 F(228570000, P_GPLL0, 3.5, 0, 0),
950 F(240000000, P_GPLL6, 4.5, 0, 0),
951 F(266670000, P_GPLL0, 3, 0, 0),
952 F(300000000, P_GPLL3, 1, 0, 0),
953 F(320000000, P_GPLL0, 2.5, 0, 0),
954 F(375000000, P_GPLL3, 1, 0, 0),
955 F(400000000, P_GPLL0, 2, 0, 0),
956 F(450000000, P_GPLL3, 1, 0, 0),
961 .cmd_rcgr = 0x59000,
975 F(19200000, P_XO, 1, 0, 0),
980 .cmd_rcgr = 0x08004,
994 .cmd_rcgr = 0x09004,
1008 .cmd_rcgr = 0x0a004,
1022 F(133330000, P_GPLL0, 6, 0, 0),
1023 F(266670000, P_GPLL0, 3, 0, 0),
1024 F(320000000, P_GPLL0, 2.5, 0, 0),
1029 .cmd_rcgr = 0x57000,
1042 F(19200000, P_XO, 1, 0, 0),
1044 F(66667000, P_GPLL0, 12, 0, 0),
1049 .cmd_rcgr = 0x52000,
1063 .cmd_rcgr = 0x53000,
1077 .cmd_rcgr = 0x5c000,
1091 F(50000000, P_GPLL0, 16, 0, 0),
1092 F(80000000, P_GPLL0, 10, 0, 0),
1093 F(100000000, P_GPLL0, 8, 0, 0),
1094 F(145450000, P_GPLL0, 5.5, 0, 0),
1095 F(160000000, P_GPLL0, 5, 0, 0),
1096 F(177780000, P_GPLL0, 4.5, 0, 0),
1097 F(200000000, P_GPLL0, 4, 0, 0),
1098 F(266670000, P_GPLL0, 3, 0, 0),
1099 F(320000000, P_GPLL0, 2.5, 0, 0),
1104 .cmd_rcgr = 0x4d014,
1117 { P_XO, 0 },
1123 { P_XO, 0 },
1135 .cmd_rcgr = 0x4d000,
1149 .cmd_rcgr = 0x4d0b8,
1163 F(64000000, P_GPLL0, 12.5, 0, 0),
1168 .cmd_rcgr = 0x44010,
1181 F(100000000, P_GPLL0, 8, 0, 0),
1182 F(200000000, P_GPLL0, 4, 0, 0),
1187 .cmd_rcgr = 0x5d000,
1200 { P_XO, 0 },
1216 F(50000000, P_GPLL0, 16, 0, 0),
1217 F(100000000, P_GPLL0, 8, 0, 0),
1218 F(177770000, P_GPLL0, 4.5, 0, 0),
1219 F(192000000, P_GPLL4, 6, 0, 0),
1220 F(200000000, P_GPLL0, 4, 0, 0),
1221 F(384000000, P_GPLL4, 3, 0, 0),
1226 .cmd_rcgr = 0x42004,
1244 F(50000000, P_GPLL0, 16, 0, 0),
1245 F(100000000, P_GPLL0, 8, 0, 0),
1246 F(177770000, P_GPLL0, 4.5, 0, 0),
1247 F(200000000, P_GPLL0, 4, 0, 0),
1252 .cmd_rcgr = 0x43004,
1266 F(80000000, P_GPLL0, 10, 0, 0),
1267 F(100000000, P_GPLL0, 8, 0, 0),
1268 F(133330000, P_GPLL0, 6, 0, 0),
1269 F(177780000, P_GPLL0, 4.5, 0, 0),
1274 F(57142857, P_GPLL0, 14, 0, 0),
1275 F(100000000, P_GPLL0, 8, 0, 0),
1276 F(133333333, P_GPLL0, 6, 0, 0),
1277 F(177777778, P_GPLL0, 4.5, 0, 0),
1282 .cmd_rcgr = 0x41010,
1295 F(133330000, P_GPLL0, 6, 0, 0),
1296 F(180000000, P_GPLL6, 6, 0, 0),
1297 F(228570000, P_GPLL0, 3.5, 0, 0),
1298 F(266670000, P_GPLL0, 3, 0, 0),
1299 F(308570000, P_GPLL6, 3.5, 0, 0),
1300 F(329140000, P_GPLL4, 3.5, 0, 0),
1301 F(360000000, P_GPLL6, 3, 0, 0),
1306 F(166150000, P_GPLL6, 6.5, 0, 0),
1307 F(240000000, P_GPLL6, 4.5, 0, 0),
1308 F(308571428, P_GPLL6, 3.5, 0, 0),
1309 F(320000000, P_GPLL0, 2.5, 0, 0),
1310 F(360000000, P_GPLL6, 3, 0, 0),
1315 .cmd_rcgr = 0x4c000,
1328 F(50000000, P_GPLL0, 16, 0, 0),
1329 F(80000000, P_GPLL0, 10, 0, 0),
1330 F(100000000, P_GPLL0, 8, 0, 0),
1331 F(133330000, P_GPLL0, 6, 0, 0),
1332 F(160000000, P_GPLL0, 5, 0, 0),
1333 F(200000000, P_GPLL0, 4, 0, 0),
1334 F(266670000, P_GPLL0, 3, 0, 0),
1335 F(308570000, P_GPLL6, 3.5, 0, 0),
1336 F(320000000, P_GPLL0, 2.5, 0, 0),
1337 F(329140000, P_GPLL4, 3.5, 0, 0),
1338 F(360000000, P_GPLL6, 3, 0, 0),
1343 F(50000000, P_GPLL0, 16, 0, 0),
1344 F(80000000, P_GPLL0, 10, 0, 0),
1345 F(100000000, P_GPLL0, 8, 0, 0),
1346 F(133333333, P_GPLL0, 6, 0, 0),
1347 F(160000000, P_GPLL0, 5, 0, 0),
1348 F(177777778, P_GPLL0, 4.5, 0, 0),
1349 F(200000000, P_GPLL0, 4, 0, 0),
1350 F(266666667, P_GPLL0, 3, 0, 0),
1351 F(308571428, P_GPLL6, 3.5, 0, 0),
1352 F(320000000, P_GPLL0, 2.5, 0, 0),
1353 F(360000000, P_GPLL6, 3, 0, 0),
1354 F(400000000, P_GPLL0, 2, 0, 0),
1355 F(432000000, P_GPLL6, 2.5, 0, 0),
1360 .cmd_rcgr = 0x58000,
1373 .cmd_rcgr = 0x58054,
1386 F(19200000, P_XO, 1, 0, 0),
1391 .cmd_rcgr = 0x4d02c,
1404 .halt_reg = 0x12018,
1407 .enable_reg = 0x4500c,
1417 .halt_reg = 0x59034,
1420 .enable_reg = 0x59034,
1421 .enable_mask = BIT(0),
1430 .halt_reg = 0x59030,
1433 .enable_reg = 0x59030,
1434 .enable_mask = BIT(0),
1443 .halt_reg = 0x01008,
1446 .enable_reg = 0x45004,
1456 .halt_reg = 0x0b008,
1459 .enable_reg = 0x45004,
1469 .halt_reg = 0x02008,
1472 .enable_reg = 0x02008,
1473 .enable_mask = BIT(0),
1487 .halt_reg = 0x03010,
1490 .enable_reg = 0x03010,
1491 .enable_mask = BIT(0),
1505 .halt_reg = 0x04020,
1508 .enable_reg = 0x04020,
1509 .enable_mask = BIT(0),
1523 .halt_reg = 0x05020,
1526 .enable_reg = 0x05020,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x0c008,
1544 .enable_reg = 0x0c008,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x0d010,
1562 .enable_reg = 0x0d010,
1563 .enable_mask = BIT(0),
1577 .halt_reg = 0x0f020,
1580 .enable_reg = 0x0f020,
1581 .enable_mask = BIT(0),
1595 .halt_reg = 0x18020,
1598 .enable_reg = 0x18020,
1599 .enable_mask = BIT(0),
1613 .halt_reg = 0x02004,
1616 .enable_reg = 0x02004,
1617 .enable_mask = BIT(0),
1631 .halt_reg = 0x0300c,
1634 .enable_reg = 0x0300c,
1635 .enable_mask = BIT(0),
1649 .halt_reg = 0x0401c,
1652 .enable_reg = 0x0401c,
1653 .enable_mask = BIT(0),
1667 .halt_reg = 0x0501c,
1670 .enable_reg = 0x0501c,
1671 .enable_mask = BIT(0),
1685 .halt_reg = 0x0c004,
1688 .enable_reg = 0x0c004,
1689 .enable_mask = BIT(0),
1703 .halt_reg = 0x0d00c,
1706 .enable_reg = 0x0d00c,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x0f01c,
1724 .enable_reg = 0x0f01c,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x1801c,
1742 .enable_reg = 0x1801c,
1743 .enable_mask = BIT(0),
1757 .halt_reg = 0x0203c,
1760 .enable_reg = 0x0203c,
1761 .enable_mask = BIT(0),
1775 .halt_reg = 0x0302c,
1778 .enable_reg = 0x0302c,
1779 .enable_mask = BIT(0),
1793 .halt_reg = 0x0c03c,
1796 .enable_reg = 0x0c03c,
1797 .enable_mask = BIT(0),
1811 .halt_reg = 0x0d02c,
1814 .enable_reg = 0x0d02c,
1815 .enable_mask = BIT(0),
1829 .halt_reg = 0x1300c,
1832 .enable_reg = 0x45004,
1842 .halt_reg = 0x56004,
1845 .enable_reg = 0x56004,
1846 .enable_mask = BIT(0),
1855 .halt_reg = 0x5101c,
1858 .enable_reg = 0x5101c,
1859 .enable_mask = BIT(0),
1873 .halt_reg = 0x51018,
1876 .enable_reg = 0x51018,
1877 .enable_mask = BIT(0),
1891 .halt_reg = 0x58040,
1894 .enable_reg = 0x58040,
1895 .enable_mask = BIT(0),
1909 .halt_reg = 0x5803c,
1912 .enable_reg = 0x5803c,
1913 .enable_mask = BIT(0),
1927 .halt_reg = 0x4e040,
1930 .enable_reg = 0x4e040,
1931 .enable_mask = BIT(0),
1945 .halt_reg = 0x4f040,
1948 .enable_reg = 0x4f040,
1949 .enable_mask = BIT(0),
1963 .halt_reg = 0x3c040,
1966 .enable_reg = 0x3c040,
1967 .enable_mask = BIT(0),
1981 .halt_reg = 0x4e03c,
1984 .enable_reg = 0x4e03c,
1985 .enable_mask = BIT(0),
1999 .halt_reg = 0x4f03c,
2002 .enable_reg = 0x4f03c,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x3c03c,
2020 .enable_reg = 0x3c03c,
2021 .enable_mask = BIT(0),
2035 .halt_reg = 0x4e048,
2038 .enable_reg = 0x4e048,
2039 .enable_mask = BIT(0),
2053 .halt_reg = 0x4f048,
2056 .enable_reg = 0x4f048,
2057 .enable_mask = BIT(0),
2071 .halt_reg = 0x3c048,
2074 .enable_reg = 0x3c048,
2075 .enable_mask = BIT(0),
2089 .halt_reg = 0x4e01c,
2092 .enable_reg = 0x4e01c,
2093 .enable_mask = BIT(0),
2107 .halt_reg = 0x4f01c,
2110 .enable_reg = 0x4f01c,
2111 .enable_mask = BIT(0),
2125 .halt_reg = 0x4e058,
2128 .enable_reg = 0x4e058,
2129 .enable_mask = BIT(0),
2143 .halt_reg = 0x4f058,
2146 .enable_reg = 0x4f058,
2147 .enable_mask = BIT(0),
2161 .halt_reg = 0x3c058,
2164 .enable_reg = 0x3c058,
2165 .enable_mask = BIT(0),
2179 .halt_reg = 0x4e050,
2182 .enable_reg = 0x4e050,
2183 .enable_mask = BIT(0),
2197 .halt_reg = 0x4f050,
2200 .enable_reg = 0x4f050,
2201 .enable_mask = BIT(0),
2215 .halt_reg = 0x3c050,
2218 .enable_reg = 0x3c050,
2219 .enable_mask = BIT(0),
2233 .halt_reg = 0x58050,
2236 .enable_reg = 0x58050,
2237 .enable_mask = BIT(0),
2251 .halt_reg = 0x58074,
2254 .enable_reg = 0x58074,
2255 .enable_mask = BIT(0),
2269 .halt_reg = 0x54018,
2272 .enable_reg = 0x54018,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x55018,
2290 .enable_reg = 0x55018,
2291 .enable_mask = BIT(0),
2305 .halt_reg = 0x50004,
2308 .enable_reg = 0x50004,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x57020,
2326 .enable_reg = 0x57020,
2327 .enable_mask = BIT(0),
2341 .halt_reg = 0x57024,
2344 .enable_reg = 0x57024,
2345 .enable_mask = BIT(0),
2359 .halt_reg = 0x57028,
2362 .enable_reg = 0x57028,
2363 .enable_mask = BIT(0),
2372 .halt_reg = 0x52018,
2375 .enable_reg = 0x52018,
2376 .enable_mask = BIT(0),
2390 .halt_reg = 0x53018,
2393 .enable_reg = 0x53018,
2394 .enable_mask = BIT(0),
2408 .halt_reg = 0x5c018,
2411 .enable_reg = 0x5c018,
2412 .enable_mask = BIT(0),
2426 .halt_reg = 0x5600c,
2429 .enable_reg = 0x5600c,
2430 .enable_mask = BIT(0),
2444 .halt_reg = 0x5a014,
2447 .enable_reg = 0x5a014,
2448 .enable_mask = BIT(0),
2462 .halt_reg = 0x58044,
2465 .enable_reg = 0x58044,
2466 .enable_mask = BIT(0),
2480 .halt_reg = 0x58048,
2483 .enable_reg = 0x58048,
2484 .enable_mask = BIT(0),
2493 .halt_reg = 0x58038,
2496 .enable_reg = 0x58038,
2497 .enable_mask = BIT(0),
2511 .halt_reg = 0x58060,
2514 .enable_reg = 0x58060,
2515 .enable_mask = BIT(0),
2529 .halt_reg = 0x58068,
2532 .enable_reg = 0x58068,
2533 .enable_mask = BIT(0),
2542 .halt_reg = 0x5805c,
2545 .enable_reg = 0x5805c,
2546 .enable_mask = BIT(0),
2560 .halt_reg = 0x12040,
2563 .enable_reg = 0x4500c,
2573 .halt_reg = 0x16024,
2576 .enable_reg = 0x45004,
2577 .enable_mask = BIT(0),
2586 .halt_reg = 0x16020,
2589 .enable_reg = 0x45004,
2599 .halt_reg = 0x1601c,
2602 .enable_reg = 0x45004,
2617 .halt_reg = 0x77004,
2620 .enable_reg = 0x77004,
2621 .enable_mask = BIT(0),
2630 .halt_reg = 0x12010,
2633 .enable_reg = 0x4500c,
2643 .halt_reg = 0x12020,
2646 .enable_reg = 0x4500c,
2656 .halt_reg = 0x12044,
2659 .enable_reg = 0x4500c,
2669 .halt_reg = 0x08000,
2672 .enable_reg = 0x08000,
2673 .enable_mask = BIT(0),
2687 .halt_reg = 0x09000,
2690 .enable_reg = 0x09000,
2691 .enable_mask = BIT(0),
2705 .halt_reg = 0x0a000,
2708 .enable_reg = 0x0a000,
2709 .enable_mask = BIT(0),
2723 .halt_reg = 0x12034,
2726 .enable_reg = 0x4500c,
2736 .halt_reg = 0x1201c,
2739 .enable_reg = 0x4500c,
2749 .halt_reg = 0x4d07c,
2752 .enable_reg = 0x4d07c,
2753 .enable_mask = BIT(0),
2762 .halt_reg = 0x4d080,
2765 .enable_reg = 0x4d080,
2766 .enable_mask = BIT(0),
2775 .halt_reg = 0x4d094,
2778 .enable_reg = 0x4d094,
2779 .enable_mask = BIT(0),
2793 .halt_reg = 0x4d0a0,
2796 .enable_reg = 0x4d0a0,
2797 .enable_mask = BIT(0),
2811 .halt_reg = 0x4d098,
2814 .enable_reg = 0x4d098,
2815 .enable_mask = BIT(0),
2829 .halt_reg = 0x4d09c,
2832 .enable_reg = 0x4d09c,
2833 .enable_mask = BIT(0),
2847 .halt_reg = 0x4d088,
2850 .enable_reg = 0x4d088,
2851 .enable_mask = BIT(0),
2865 .halt_reg = 0x4d084,
2868 .enable_reg = 0x4d084,
2869 .enable_mask = BIT(0),
2883 .halt_reg = 0x4d0a4,
2886 .enable_reg = 0x4d0a4,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x4d090,
2904 .enable_reg = 0x4d090,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x49000,
2922 .enable_reg = 0x49000,
2923 .enable_mask = BIT(0),
2932 .halt_reg = 0x49004,
2935 .enable_reg = 0x49004,
2936 .enable_mask = BIT(0),
2945 .halt_reg = 0x59028,
2948 .enable_reg = 0x59028,
2949 .enable_mask = BIT(0),
2958 .halt_reg = 0x5904c,
2961 .enable_reg = 0x5904c,
2962 .enable_mask = BIT(0),
2976 .halt_reg = 0x59020,
2979 .enable_reg = 0x59020,
2980 .enable_mask = BIT(0),
2994 .halt_reg = 0x59040,
2997 .enable_reg = 0x59040,
2998 .enable_mask = BIT(0),
3007 .halt_reg = 0x4400c,
3010 .enable_reg = 0x4400c,
3011 .enable_mask = BIT(0),
3025 .halt_reg = 0x44004,
3028 .enable_reg = 0x44004,
3029 .enable_mask = BIT(0),
3038 .halt_reg = 0x13004,
3041 .enable_reg = 0x45004,
3051 .halt_reg = 0x29084,
3054 .enable_reg = 0x45004,
3064 .halt_reg = 0x5d014,
3067 .enable_reg = 0x5d014,
3068 .enable_mask = BIT(0),
3082 .halt_reg = 0x4201c,
3085 .enable_reg = 0x4201c,
3086 .enable_mask = BIT(0),
3095 .halt_reg = 0x4301c,
3098 .enable_reg = 0x4301c,
3099 .enable_mask = BIT(0),
3108 .halt_reg = 0x42018,
3111 .enable_reg = 0x42018,
3112 .enable_mask = BIT(0),
3126 .halt_reg = 0x43018,
3129 .enable_reg = 0x43018,
3130 .enable_mask = BIT(0),
3144 .halt_reg = 0x12038,
3147 .enable_reg = 0x4500c,
3157 .halt_reg = 0x4102c,
3159 .enable_reg = 0x4102c,
3160 .enable_mask = BIT(0),
3169 .halt_reg = 0x41008,
3171 .enable_reg = 0x41008,
3172 .enable_mask = BIT(0),
3181 .halt_reg = 0x41030,
3183 .enable_reg = 0x41030,
3184 .enable_mask = BIT(0),
3193 .halt_reg = 0x41004,
3195 .enable_reg = 0x41004,
3196 .enable_mask = BIT(0),
3210 .halt_reg = 0x4c020,
3213 .enable_reg = 0x4c020,
3214 .enable_mask = BIT(0),
3223 .halt_reg = 0x4c024,
3226 .enable_reg = 0x4c024,
3227 .enable_mask = BIT(0),
3236 .halt_reg = 0x4c02c,
3239 .enable_reg = 0x4c02c,
3240 .enable_mask = BIT(0),
3254 .halt_reg = 0x4c01c,
3257 .enable_reg = 0x4c01c,
3258 .enable_mask = BIT(0),
3272 .halt_reg = 0x12014,
3275 .enable_reg = 0x4500c,
3285 .halt_reg = 0x12090,
3288 .enable_reg = 0x4500c,
3298 .halt_reg = 0x1203c,
3301 .enable_reg = 0x4500c,
3311 .gdscr = 0x4c018,
3312 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3321 .gdscr = 0x4c028,
3322 .cxcs = (unsigned int []){ 0x4c02c },
3332 .gdscr = 0x4d078,
3333 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3342 .gdscr = 0x5701c,
3343 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3352 .gdscr = 0x58034,
3353 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3362 .gdscr = 0x5806c,
3363 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3372 .gdscr = 0x5901c,
3373 .clamp_io_ctrl = 0x5b00c,
3374 .cxcs = (unsigned int []){ 0x59000, 0x59020 },
3384 .gdscr = 0x5901c,
3385 .clamp_io_ctrl = 0x5b00c,
3386 .cxcs = (unsigned int []){ 0x59000 },
3396 .gdscr = 0x59044,
3397 .cxcs = (unsigned int []){ 0x59020 },
3406 .gdscr = 0x58078,
3407 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3768 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3769 [GCC_MSS_BCR] = { 0x71000 },
3770 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
3771 [GCC_USB_HS_BCR] = { 0x41000 },
3772 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
3779 .max_register = 0x80000,