Lines Matching +full:0 +full:x26004
37 .offset = 0x21000,
40 .enable_reg = 0x45000,
41 .enable_mask = BIT(0),
55 .offset = 0x21000,
67 { P_XO, 0 },
77 .l_reg = 0x20004,
78 .m_reg = 0x20008,
79 .n_reg = 0x2000c,
80 .config_reg = 0x20010,
81 .mode_reg = 0x20000,
82 .status_reg = 0x2001c,
95 .enable_reg = 0x45000,
106 { P_XO, 0 },
120 .offset = 0x25000,
123 .enable_reg = 0x45000,
138 .offset = 0x25000,
150 { P_XO, 0 },
162 { P_XO, 0 },
176 F(19200000, P_XO, 1, 0, 0),
177 F(50000000, P_GPLL0, 16, 0, 0),
178 F(100000000, P_GPLL0, 8, 0, 0),
183 .cmd_rcgr = 0x46000,
196 .l_reg = 0x23004,
197 .m_reg = 0x23008,
198 .n_reg = 0x2300c,
199 .config_reg = 0x23010,
200 .mode_reg = 0x23000,
201 .status_reg = 0x2301c,
214 .enable_reg = 0x45000,
225 { P_XO, 0 },
237 F(19200000, P_XO, 1, 0, 0),
238 F(50000000, P_GPLL0, 16, 0, 0),
239 F(100000000, P_GPLL0, 8, 0, 0),
244 .cmd_rcgr = 0x27000,
258 .cmd_rcgr = 0x26004,
270 F(19200000, P_XO, 1, 0, 0),
271 F(50000000, P_GPLL0, 16, 0, 0),
276 .cmd_rcgr = 0x200c,
290 F(4800000, P_XO, 4, 0, 0),
291 F(9600000, P_XO, 2, 0, 0),
293 F(19200000, P_XO, 1, 0, 0),
295 F(50000000, P_GPLL0, 16, 0, 0),
300 .cmd_rcgr = 0x2024,
314 .cmd_rcgr = 0x3000,
327 .cmd_rcgr = 0x3014,
341 .cmd_rcgr = 0x4000,
354 .cmd_rcgr = 0x4024,
368 .cmd_rcgr = 0x5000,
381 .cmd_rcgr = 0x5024,
395 .cmd_rcgr = 0x6000,
408 .cmd_rcgr = 0x6024,
422 .cmd_rcgr = 0x7000,
435 .cmd_rcgr = 0x7024,
453 F(19200000, P_XO, 1, 0, 0),
468 .cmd_rcgr = 0x2044,
482 .cmd_rcgr = 0x3034,
496 .cmd_rcgr = 0x4044,
510 .cmd_rcgr = 0x5044,
524 .cmd_rcgr = 0x6044,
538 .cmd_rcgr = 0x6044,
552 F(50000000, P_GPLL0, 16, 0, 0),
553 F(80000000, P_GPLL0, 10, 0, 0),
554 F(100000000, P_GPLL0, 8, 0, 0),
555 F(160000000, P_GPLL0, 5, 0, 0),
560 .cmd_rcgr = 0x16004,
573 F(19200000, P_XO, 1, 0, 0),
578 .cmd_rcgr = 0x8004,
592 .cmd_rcgr = 0x09004,
606 .cmd_rcgr = 0x0a004,
620 F(64000000, P_GPLL0, 12.5, 0, 0),
625 .cmd_rcgr = 0x44010,
642 F(50000000, P_GPLL0, 16, 0, 0),
643 F(100000000, P_GPLL0, 8, 0, 0),
644 F(177770000, P_GPLL0, 4.5, 0, 0),
645 F(200000000, P_GPLL0, 4, 0, 0),
650 .cmd_rcgr = 0x42004,
664 .cmd_rcgr = 0x43004,
678 F(155000000, P_GPLL2, 6, 0, 0),
679 F(310000000, P_GPLL2, 3, 0, 0),
680 F(400000000, P_GPLL0, 2, 0, 0),
685 .cmd_rcgr = 0x1207c,
698 F(19200000, P_XO, 1, 0, 0),
699 F(57140000, P_GPLL0, 14, 0, 0),
700 F(69565000, P_GPLL0, 11.5, 0, 0),
701 F(133330000, P_GPLL0, 6, 0, 0),
702 F(177778000, P_GPLL0, 4.5, 0, 0),
707 .cmd_rcgr = 0x41010,
720 F(480000000, P_GPLL2, 1, 0, 0),
725 .cmd_rcgr = 0x3d018,
738 F(9600000, P_XO, 2, 0, 0),
743 .cmd_rcgr = 0x3d030,
756 F(19200000, P_XO, 1, 0, 0),
757 F(57140000, P_GPLL0, 14, 0, 0),
758 F(133330000, P_GPLL0, 6, 0, 0),
759 F(177778000, P_GPLL0, 4.5, 0, 0),
764 .cmd_rcgr = 0x3d000,
777 .halt_reg = 0x1008,
780 .enable_reg = 0x45004,
792 .halt_reg = 0x1004,
794 .enable_reg = 0x1004,
795 .enable_mask = BIT(0),
809 .halt_reg = 0x2008,
811 .enable_reg = 0x2008,
812 .enable_mask = BIT(0),
824 .halt_reg = 0x2004,
826 .enable_reg = 0x2004,
827 .enable_mask = BIT(0),
839 .halt_reg = 0x3010,
841 .enable_reg = 0x3010,
842 .enable_mask = BIT(0),
854 .halt_reg = 0x300c,
856 .enable_reg = 0x300c,
857 .enable_mask = BIT(0),
869 .halt_reg = 0x4020,
871 .enable_reg = 0x4020,
872 .enable_mask = BIT(0),
884 .halt_reg = 0x401c,
886 .enable_reg = 0x401c,
887 .enable_mask = BIT(0),
899 .halt_reg = 0x5020,
901 .enable_reg = 0x5020,
902 .enable_mask = BIT(0),
914 .halt_reg = 0x501c,
916 .enable_reg = 0x501c,
917 .enable_mask = BIT(0),
929 .halt_reg = 0x6020,
931 .enable_reg = 0x6020,
932 .enable_mask = BIT(0),
944 .halt_reg = 0x601c,
946 .enable_reg = 0x601c,
947 .enable_mask = BIT(0),
959 .halt_reg = 0x7020,
961 .enable_reg = 0x7020,
962 .enable_mask = BIT(0),
974 .halt_reg = 0x701c,
976 .enable_reg = 0x701c,
977 .enable_mask = BIT(0),
989 .halt_reg = 0x203c,
991 .enable_reg = 0x203c,
992 .enable_mask = BIT(0),
1004 .halt_reg = 0x302c,
1006 .enable_reg = 0x302c,
1007 .enable_mask = BIT(0),
1019 .halt_reg = 0x403c,
1021 .enable_reg = 0x403c,
1022 .enable_mask = BIT(0),
1034 .halt_reg = 0x503c,
1036 .enable_reg = 0x503c,
1037 .enable_mask = BIT(0),
1049 .halt_reg = 0x603c,
1051 .enable_reg = 0x603c,
1052 .enable_mask = BIT(0),
1064 .halt_reg = 0x703c,
1066 .enable_reg = 0x703c,
1067 .enable_mask = BIT(0),
1079 .halt_reg = 0x1300c,
1082 .enable_reg = 0x45004,
1094 .halt_reg = 0x16024,
1097 .enable_reg = 0x45004,
1098 .enable_mask = BIT(0),
1110 .halt_reg = 0x16020,
1113 .enable_reg = 0x45004,
1126 .halt_reg = 0x1601c,
1129 .enable_reg = 0x45004,
1142 .halt_reg = 0x08000,
1144 .enable_reg = 0x08000,
1145 .enable_mask = BIT(0),
1157 .halt_reg = 0x09000,
1159 .enable_reg = 0x09000,
1160 .enable_mask = BIT(0),
1172 .halt_reg = 0x0a000,
1174 .enable_reg = 0x0a000,
1175 .enable_mask = BIT(0),
1187 .halt_reg = 0x49000,
1189 .enable_reg = 0x49000,
1190 .enable_mask = BIT(0),
1202 .halt_reg = 0x4400c,
1204 .enable_reg = 0x4400c,
1205 .enable_mask = BIT(0),
1217 .halt_reg = 0x44004,
1219 .enable_reg = 0x44004,
1220 .enable_mask = BIT(0),
1232 .halt_reg = 0x13004,
1235 .enable_reg = 0x45004,
1248 .halt_reg = 0x4201c,
1250 .enable_reg = 0x4201c,
1251 .enable_mask = BIT(0),
1263 .halt_reg = 0x42018,
1265 .enable_reg = 0x42018,
1266 .enable_mask = BIT(0),
1278 .halt_reg = 0x4301c,
1280 .enable_reg = 0x4301c,
1281 .enable_mask = BIT(0),
1293 .halt_reg = 0x43018,
1295 .enable_reg = 0x43018,
1296 .enable_mask = BIT(0),
1308 .cmd_rcgr = 0x32004,
1321 .halt_reg = 0x49004,
1323 .enable_reg = 0x49004,
1324 .enable_mask = BIT(0),
1336 .halt_reg = 0x12018,
1339 .enable_reg = 0x4500c,
1351 .halt_reg = 0x12038,
1354 .enable_reg = 0x4500c,
1367 .halt_reg = 0x29084,
1370 .enable_reg = 0x45004,
1384 .halt_reg = 0x4102c,
1386 .enable_reg = 0x4102c,
1387 .enable_mask = BIT(0),
1401 .halt_reg = 0x41030,
1404 .enable_reg = 0x41030,
1405 .enable_mask = BIT(0),
1417 .halt_reg = 0x41008,
1419 .enable_reg = 0x41008,
1420 .enable_mask = BIT(0),
1432 .halt_reg = 0x41004,
1434 .enable_reg = 0x41004,
1435 .enable_mask = BIT(0),
1447 .halt_reg = 0x4601c,
1450 .enable_reg = 0x45004,
1462 .halt_reg = 0x4601c,
1465 .enable_reg = 0x45004,
1567 [USB_HS_HSIC_BCR] = { 0x3d05c },
1568 [GCC_MSS_RESTART] = { 0x3e000 },
1569 [USB_HS_BCR] = { 0x41000 },
1570 [USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
1571 [QUSB2_PHY_BCR] = { 0x4103c },
1578 .max_register = 0x80000,
1605 regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0)); in gcc_mdm9607_probe()