Lines Matching +full:0 +full:x17080
58 { P_XO, 0 },
70 .offset = 0x20000,
73 .enable_reg = 0x0b000,
74 .enable_mask = BIT(0),
98 .offset = 0x20000,
112 .offset = 0x22000,
115 .enable_reg = 0x0b000,
127 .offset = 0x22000,
141 .offset = 0x21000,
144 .enable_reg = 0x0b000,
156 .offset = 0x21000,
170 .halt_reg = 0x3400c,
172 .enable_reg = 0x3400c,
191 { P_XO, 0 },
202 { P_XO, 0 },
213 { P_XO, 0 },
226 { P_XO, 0 },
240 { P_XO, 0 },
253 { P_XO, 0 },
266 { P_XO, 0 },
282 { P_XO, 0 },
295 { P_XO, 0 },
309 { P_XO, 0 },
321 { P_USB3PHY_0_PIPE, 0 },
334 { P_XO, 0 },
348 { P_XO, 0 },
362 { P_XO, 0 },
375 { P_XO, 0 },
389 { P_XO, 0 },
404 { P_XO, 0 },
411 F(24000000, P_XO, 1, 0, 0),
412 F(50000000, P_GPLL0, 16, 0, 0),
413 F(100000000, P_GPLL0, 8, 0, 0),
418 .cmd_rcgr = 0x2400c,
431 F(533000000, P_GPLL0, 1.5, 0, 0),
436 .cmd_rcgr = 0x24004,
449 F(9600000, P_XO, 2.5, 0, 0),
450 F(24000000, P_XO, 1, 0, 0),
451 F(50000000, P_GPLL0, 16, 0, 0),
456 .cmd_rcgr = 0x02018,
470 F(4800000, P_XO, 5, 0, 0),
473 F(24000000, P_XO, 1, 0, 0),
475 F(50000000, P_GPLL0, 16, 0, 0),
480 .cmd_rcgr = 0x02004,
494 .cmd_rcgr = 0x03018,
507 .cmd_rcgr = 0x03004,
521 .cmd_rcgr = 0x04018,
534 .cmd_rcgr = 0x04004,
548 .cmd_rcgr = 0x05018,
561 .cmd_rcgr = 0x05004,
575 .cmd_rcgr = 0x06018,
588 .cmd_rcgr = 0x06004,
602 .cmd_rcgr = 0x07018,
615 .cmd_rcgr = 0x07004,
632 F(24000000, P_XO, 1, 0, 0),
642 F(64000000, P_GPLL0, 12.5, 0, 0),
647 .cmd_rcgr = 0x0202c,
661 .cmd_rcgr = 0x0302c,
675 .cmd_rcgr = 0x0402c,
689 .cmd_rcgr = 0x0502c,
703 .cmd_rcgr = 0x0602c,
717 .cmd_rcgr = 0x0702c,
731 F(160000000, P_GPLL0, 5, 0, 0),
736 .cmd_rcgr = 0x16004,
749 .halt_reg = 0x1600c,
752 .enable_reg = 0x0b004,
766 .halt_reg = 0x24018,
769 .enable_reg = 0x0b004,
770 .enable_mask = BIT(0),
784 .halt_reg = 0x2401c,
787 .enable_reg = 0x0b004,
802 .halt_reg = 0x2024,
804 .enable_reg = 0x2024,
805 .enable_mask = BIT(0),
819 .halt_reg = 0x02020,
821 .enable_reg = 0x02020,
822 .enable_mask = BIT(0),
836 .halt_reg = 0x03024,
838 .enable_reg = 0x03024,
839 .enable_mask = BIT(0),
853 .halt_reg = 0x03020,
855 .enable_reg = 0x03020,
856 .enable_mask = BIT(0),
870 .halt_reg = 0x04024,
872 .enable_reg = 0x04024,
873 .enable_mask = BIT(0),
887 .halt_reg = 0x04020,
889 .enable_reg = 0x04020,
890 .enable_mask = BIT(0),
904 .halt_reg = 0x05024,
906 .enable_reg = 0x05024,
907 .enable_mask = BIT(0),
921 .halt_reg = 0x05020,
923 .enable_reg = 0x05020,
924 .enable_mask = BIT(0),
938 .halt_reg = 0x06024,
940 .enable_reg = 0x06024,
941 .enable_mask = BIT(0),
955 .halt_reg = 0x06020,
957 .enable_reg = 0x06020,
958 .enable_mask = BIT(0),
972 .halt_reg = 0x07024,
974 .enable_reg = 0x07024,
975 .enable_mask = BIT(0),
989 .halt_reg = 0x07020,
991 .enable_reg = 0x07020,
992 .enable_mask = BIT(0),
1006 .halt_reg = 0x02040,
1008 .enable_reg = 0x02040,
1009 .enable_mask = BIT(0),
1023 .halt_reg = 0x03040,
1025 .enable_reg = 0x03040,
1026 .enable_mask = BIT(0),
1040 .halt_reg = 0x04054,
1042 .enable_reg = 0x04054,
1043 .enable_mask = BIT(0),
1057 .halt_reg = 0x05040,
1059 .enable_reg = 0x05040,
1060 .enable_mask = BIT(0),
1074 .halt_reg = 0x06040,
1076 .enable_reg = 0x06040,
1077 .enable_mask = BIT(0),
1091 .halt_reg = 0x07040,
1093 .enable_reg = 0x07040,
1094 .enable_mask = BIT(0),
1108 F(240000000, P_GPLL4, 5, 0, 0),
1113 .cmd_rcgr = 0x28018,
1126 .halt_reg = 0x28038,
1128 .enable_reg = 0x28038,
1129 .enable_mask = BIT(0),
1143 .halt_reg = 0x2e07c,
1145 .enable_reg = 0x2e07c,
1146 .enable_mask = BIT(0),
1160 .cmd_rcgr = 0x29018,
1173 .halt_reg = 0x29038,
1175 .enable_reg = 0x29038,
1176 .enable_mask = BIT(0),
1190 .halt_reg = 0x2e08c,
1192 .enable_reg = 0x2e08c,
1193 .enable_mask = BIT(0),
1207 F(342857143, P_GPLL4, 3.5, 0, 0),
1212 .cmd_rcgr = 0x2a018,
1225 .halt_reg = 0x2a038,
1227 .enable_reg = 0x2a038,
1228 .enable_mask = BIT(0),
1242 .halt_reg = 0x2e080,
1244 .enable_reg = 0x2e080,
1245 .enable_mask = BIT(0),
1259 .cmd_rcgr = 0x2b018,
1272 .halt_reg = 0x2b038,
1274 .enable_reg = 0x2b038,
1275 .enable_mask = BIT(0),
1289 .halt_reg = 0x2e090,
1291 .enable_reg = 0x2e090,
1292 .enable_mask = BIT(0),
1306 .cmd_rcgr = 0x28020,
1319 .halt_reg = 0x2803c,
1321 .enable_reg = 0x2803c,
1322 .enable_mask = BIT(0),
1336 .halt_reg = 0x28040,
1338 .enable_reg = 0x28040,
1339 .enable_mask = BIT(0),
1353 .halt_reg = 0x2e048,
1355 .enable_reg = 0x2e048,
1356 .enable_mask = BIT(0),
1370 .cmd_rcgr = 0x29020,
1383 .halt_reg = 0x2903c,
1385 .enable_reg = 0x2903c,
1386 .enable_mask = BIT(0),
1400 .halt_reg = 0x29040,
1402 .enable_reg = 0x29040,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0x2e04c,
1419 .enable_reg = 0x2e04c,
1420 .enable_mask = BIT(0),
1434 .cmd_rcgr = 0x2a020,
1447 .halt_reg = 0x2a03c,
1449 .enable_reg = 0x2a03c,
1450 .enable_mask = BIT(0),
1464 .halt_reg = 0x2a040,
1466 .enable_reg = 0x2a040,
1467 .enable_mask = BIT(0),
1481 .halt_reg = 0x2e050,
1483 .enable_reg = 0x2e050,
1484 .enable_mask = BIT(0),
1498 .cmd_rcgr = 0x2b020,
1511 .halt_reg = 0x2b03c,
1513 .enable_reg = 0x2b03c,
1514 .enable_mask = BIT(0),
1528 .halt_reg = 0x2b040,
1530 .enable_reg = 0x2b040,
1531 .enable_mask = BIT(0),
1545 .halt_reg = 0x2e054,
1547 .enable_reg = 0x2e054,
1548 .enable_mask = BIT(0),
1562 .reg = 0x28064,
1576 .halt_reg = 0x28044,
1579 .enable_reg = 0x28044,
1580 .enable_mask = BIT(0),
1594 .reg = 0x29064,
1608 .halt_reg = 0x29044,
1611 .enable_reg = 0x29044,
1612 .enable_mask = BIT(0),
1626 .reg = 0x2a064,
1640 .halt_reg = 0x2a044,
1643 .enable_reg = 0x2a044,
1644 .enable_mask = BIT(0),
1658 .reg = 0x2b064,
1672 .halt_reg = 0x2b044,
1675 .enable_reg = 0x2b044,
1676 .enable_mask = BIT(0),
1690 F(24000000, P_XO, 1, 0, 0),
1691 F(100000000, P_GPLL0, 8, 0, 0),
1696 .cmd_rcgr = 0x28028,
1709 .halt_reg = 0x28028,
1711 .enable_reg = 0x28028,
1727 .cmd_rcgr = 0x29028,
1740 .halt_reg = 0x29028,
1742 .enable_reg = 0x29028,
1757 .cmd_rcgr = 0x2a028,
1770 .halt_reg = 0x2a028,
1772 .enable_reg = 0x2a028,
1787 .cmd_rcgr = 0x2b028,
1800 .halt_reg = 0x2b028,
1802 .enable_reg = 0x2b028,
1822 .cmd_rcgr = 0x28004,
1836 .halt_reg = 0x28034,
1838 .enable_reg = 0x28034,
1839 .enable_mask = BIT(0),
1853 .halt_reg = 0x29034,
1855 .enable_reg = 0x29034,
1856 .enable_mask = BIT(0),
1870 .halt_reg = 0x2a034,
1872 .enable_reg = 0x2a034,
1873 .enable_mask = BIT(0),
1887 .halt_reg = 0x2b034,
1889 .enable_reg = 0x2b034,
1890 .enable_mask = BIT(0),
1904 F(24000000, P_XO, 1, 0, 0),
1909 .cmd_rcgr = 0x2c018,
1923 .halt_reg = 0x2c048,
1925 .enable_reg = 0x2c048,
1926 .enable_mask = BIT(0),
1940 F(100000000, P_GPLL0, 8, 0, 0),
1941 F(200000000, P_GPLL0, 4, 0, 0),
1946 .cmd_rcgr = 0x2c004,
1960 .halt_reg = 0x2c044,
1962 .enable_reg = 0x2c044,
1963 .enable_mask = BIT(0),
1977 .halt_reg = 0x2e058,
1979 .enable_reg = 0x2e058,
1980 .enable_mask = BIT(0),
1994 .halt_reg = 0x2e084,
1996 .enable_reg = 0x2e084,
1997 .enable_mask = BIT(0),
2011 F(24000000, P_XO, 1, 0, 0),
2017 .cmd_rcgr = 0x2c02c,
2031 .reg = 0x2c040,
2032 .shift = 0,
2046 .halt_reg = 0x2c04c,
2048 .enable_reg = 0x2c04c,
2049 .enable_mask = BIT(0),
2063 .reg = 0x2C074,
2079 .halt_reg = 0x2c054,
2082 .enable_reg = 0x2c054,
2083 .enable_mask = BIT(0),
2097 .halt_reg = 0x2c058,
2099 .enable_reg = 0x2c058,
2100 .enable_mask = BIT(0),
2118 F(96000000, P_GPLL2, 12, 0, 0),
2119 F(177777778, P_GPLL0, 4.5, 0, 0),
2120 F(192000000, P_GPLL2, 6, 0, 0),
2121 F(384000000, P_GPLL2, 3, 0, 0),
2122 F(400000000, P_GPLL0, 2, 0, 0),
2127 .cmd_rcgr = 0x33004,
2141 .halt_reg = 0x3302c,
2143 .enable_reg = 0x3302c,
2144 .enable_mask = BIT(0),
2158 F(150000000, P_GPLL4, 8, 0, 0),
2159 F(300000000, P_GPLL4, 4, 0, 0),
2164 .cmd_rcgr = 0x33018,
2178 .halt_reg = 0x33030,
2180 .enable_reg = 0x33030,
2181 .enable_mask = BIT(0),
2195 F(24000000, P_XO, 1, 0, 0),
2196 F(50000000, P_GPLL0, 16, 0, 0),
2197 F(80000000, P_GPLL0, 10, 0, 0),
2198 F(100000000, P_GPLL0, 8, 0, 0),
2203 .cmd_rcgr = 0x31004,
2217 .halt_reg = 0x16010,
2220 .enable_reg = 0xb004,
2234 .halt_reg = 0x16014,
2237 .enable_reg = 0xb004,
2251 .halt_reg = 0x1702c,
2253 .enable_reg = 0x1702c,
2254 .enable_mask = BIT(0),
2268 .halt_reg = 0x17030,
2270 .enable_reg = 0x17030,
2271 .enable_mask = BIT(0),
2285 .halt_reg = 0x17034,
2287 .enable_reg = 0x17034,
2288 .enable_mask = BIT(0),
2302 .halt_reg = 0x17080,
2304 .enable_reg = 0x17080,
2305 .enable_mask = BIT(0),
2319 .halt_reg = 0x2d064,
2321 .enable_reg = 0x2d064,
2322 .enable_mask = BIT(0),
2336 .halt_reg = 0x2d068,
2338 .enable_reg = 0x2d068,
2339 .enable_mask = BIT(0),
2353 .halt_reg = 0x32010,
2355 .enable_reg = 0x32010,
2356 .enable_mask = BIT(0),
2370 .halt_reg = 0x32014,
2372 .enable_reg = 0x32014,
2373 .enable_mask = BIT(0),
2387 .halt_reg = 0x01004,
2390 .enable_reg = 0x0b004,
2405 .halt_reg = 0x17040,
2407 .enable_reg = 0x17040,
2408 .enable_mask = BIT(0),
2422 .halt_reg = 0x13024,
2425 .enable_reg = 0x0b004,
2440 .halt_reg = 0x1704c,
2442 .enable_reg = 0x1704c,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x1705c,
2459 .enable_reg = 0x1705c,
2460 .enable_mask = BIT(0),
2474 .halt_reg = 0x1706c,
2476 .enable_reg = 0x1706c,
2477 .enable_mask = BIT(0),
2491 .halt_reg = 0x3a004,
2493 .enable_reg = 0x3a004,
2494 .enable_mask = BIT(0),
2508 .halt_reg = 0x3a00c,
2510 .enable_reg = 0x3a00c,
2511 .enable_mask = BIT(0),
2525 .halt_reg = 0x28030,
2527 .enable_reg = 0x28030,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x29030,
2544 .enable_reg = 0x29030,
2545 .enable_mask = BIT(0),
2559 .halt_reg = 0x2a030,
2561 .enable_reg = 0x2a030,
2562 .enable_mask = BIT(0),
2576 .halt_reg = 0x2b030,
2578 .enable_reg = 0x2b030,
2579 .enable_mask = BIT(0),
2593 .halt_reg = 0x2c05c,
2595 .enable_reg = 0x2c05c,
2596 .enable_mask = BIT(0),
2610 .halt_reg = 0x33034,
2612 .enable_reg = 0x33034,
2613 .enable_mask = BIT(0),
2627 F(24000000, P_XO, 1, 0, 0),
2628 F(133333333, P_GPLL0, 6, 0, 0),
2629 F(200000000, P_GPLL0, 4, 0, 0),
2630 F(342850000, P_GPLL4, 3.5, 0, 0),
2635 .cmd_rcgr = 0x2e004,
2649 .halt_reg = 0x17028,
2651 .enable_reg = 0x17028,
2652 .enable_mask = BIT(0),
2666 .halt_reg = 0x1707c,
2668 .enable_reg = 0x1707c,
2669 .enable_mask = BIT(0),
2683 .halt_reg = 0x2d060,
2685 .enable_reg = 0x2d060,
2686 .enable_mask = BIT(0),
2700 F(24000000, P_XO, 1, 0, 0),
2701 F(133333333, P_GPLL0, 6, 0, 0),
2706 .cmd_rcgr = 0x25030,
2719 F(24000000, P_XO, 1, 0, 0),
2720 F(133333333, P_GPLL0, 6, 0, 0),
2721 F(266666667, P_GPLL0, 3, 0, 0),
2726 .cmd_rcgr = 0x25078,
2739 F(240000000, P_GPLL4, 5, 0, 0),
2744 .cmd_rcgr = 0x2d004,
2757 .halt_reg = 0x17014,
2759 .enable_reg = 0x17014,
2760 .enable_mask = BIT(0),
2774 .halt_reg = 0x2d038,
2776 .enable_reg = 0x2d038,
2777 .enable_mask = BIT(0),
2791 .halt_reg = 0x2e038,
2793 .enable_reg = 0x2e038,
2794 .enable_mask = BIT(0),
2808 .halt_reg = 0x31024,
2810 .enable_reg = 0x31024,
2811 .enable_mask = BIT(0),
2839 .halt_reg = 0x30004,
2841 .enable_reg = 0x30004,
2842 .enable_mask = BIT(0),
2856 .halt_reg = 0x2d06c,
2858 .enable_reg = 0x2d06c,
2859 .enable_mask = BIT(0),
2873 F(24000000, P_XO, 1, 0, 0),
2874 F(200000000, P_GPLL0, 4, 0, 0),
2879 .cmd_rcgr = 0x2d00c,
2892 .halt_reg = 0x2d03c,
2894 .enable_reg = 0x2d03c,
2895 .enable_mask = BIT(0),
2909 .halt_reg = 0x2e034,
2911 .enable_reg = 0x2e034,
2912 .enable_mask = BIT(0),
2926 F(300000000, P_GPLL4, 4, 0, 0),
2931 .cmd_rcgr = 0x2d014,
2944 .halt_reg = 0x2d040,
2946 .enable_reg = 0x2d040,
2947 .enable_mask = BIT(0),
2961 F(600000000, P_GPLL4, 2, 0, 0),
2966 .cmd_rcgr = 0x2d01c,
2993 .halt_reg = 0x2d044,
2995 .enable_reg = 0x2d044,
2996 .enable_mask = BIT(0),
3010 F(24000000, P_XO, 1, 0, 0),
3015 .cmd_rcgr = 0x17090,
3029 .cmd_rcgr = 0x17088,
3043 .halt_reg = 0x2d078,
3045 .enable_reg = 0x2d078,
3046 .enable_mask = BIT(0),
3073 .halt_reg = 0x2d04c,
3075 .enable_reg = 0x2d04c,
3076 .enable_mask = BIT(0),
3103 .halt_reg = 0x17018,
3105 .enable_reg = 0x17018,
3106 .enable_mask = BIT(0),
3120 .halt_reg = 0x2d050,
3122 .enable_reg = 0x2d050,
3123 .enable_mask = BIT(0),
3150 .halt_reg = 0x2d054,
3152 .enable_reg = 0x2d054,
3153 .enable_mask = BIT(0),
3167 .halt_reg = 0x2d058,
3169 .enable_reg = 0x2d058,
3170 .enable_mask = BIT(0),
3184 .halt_reg = 0x2d05c,
3186 .enable_reg = 0x2d05c,
3187 .enable_mask = BIT(0),
3214 .halt_reg = 0x2d048,
3216 .enable_reg = 0x2d048,
3217 .enable_mask = BIT(0),
3231 F(24000000, P_XO, 1, 0, 0),
3232 F(100000000, P_GPLL0, 8, 0, 0),
3233 F(200000000, P_GPLL0, 4, 0, 0),
3234 F(320000000, P_GPLL0, 2.5, 0, 0),
3235 F(400000000, P_GPLL0, 2, 0, 0),
3240 .cmd_rcgr = 0x32004,
3253 .halt_reg = 0x3200c,
3255 .enable_reg = 0x3200c,
3256 .enable_mask = BIT(0),
3270 F(533333333, P_GPLL0, 1.5, 0, 0),
3275 .cmd_rcgr = 0x25004,
3288 F(342857143, P_GPLL4, 3.5, 0, 0),
3293 { P_XO, 0 },
3300 .cmd_rcgr = 0x25028,
3313 F(533333333, P_GPLL0, 1.5, 0, 0),
3318 .cmd_rcgr = 0x17004,
3331 .halt_reg = 0x17024,
3333 .enable_reg = 0x17024,
3334 .enable_mask = BIT(0),
3348 .halt_reg = 0x17084,
3350 .enable_reg = 0x17084,
3351 .enable_mask = BIT(0),
3365 .halt_reg = 0x12040,
3367 .enable_reg = 0xb00c,
3382 .halt_reg = 0x19014,
3384 .enable_reg = 0x19014,
3385 .enable_mask = BIT(0),
3399 F(133333333, P_GPLL0, 6, 0, 0),
3404 .cmd_rcgr = 0x2700c,
3417 .cmd_rcgr = 0x27004,
3430 F(24000000, P_XO, 1, 0, 0),
3431 F(100000000, P_GPLL0, 8, 0, 0),
3436 .cmd_rcgr = 0x1c004,
3449 .halt_reg = 0x1c00c,
3451 .enable_reg = 0x1c00c,
3452 .enable_mask = BIT(0),
3466 F(24000000, P_XO, 1, 0, 0),
3467 F(200000000, P_GPLL0, 4, 0, 0),
3472 .cmd_rcgr = 0x8004,
3485 .cmd_rcgr = 0x9004,
3498 .cmd_rcgr = 0xa004,
3511 .halt_reg = 0x34004,
3513 .enable_reg = 0x34004,
3526 .halt_reg = 0x17074,
3528 .enable_reg = 0x17074,
3529 .enable_mask = BIT(0),
3543 .halt_reg = 0x34018,
3545 .enable_reg = 0x34018,
3546 .enable_mask = BIT(0),
3560 .halt_reg = 0x17048,
3562 .enable_reg = 0x17048,
3563 .enable_mask = BIT(0),
3577 .halt_reg = 0x17058,
3579 .enable_reg = 0x17058,
3580 .enable_mask = BIT(0),
3594 .halt_reg = 0x17068,
3596 .enable_reg = 0x17068,
3597 .enable_mask = BIT(0),
3611 .halt_reg = 0x3a008,
3613 .enable_reg = 0x3a008,
3614 .enable_mask = BIT(0),
3642 .halt_reg = 0x1701c,
3644 .enable_reg = 0x1701c,
3645 .enable_mask = BIT(0),
3659 .halt_reg = 0x17020,
3661 .enable_reg = 0x17020,
3662 .enable_mask = BIT(0),
3676 .halt_reg = 0x3401c,
3678 .enable_reg = 0x3401c,
3679 .enable_mask = BIT(0),
3902 [GCC_ADSS_BCR] = { 0x1c000, 0 },
3903 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
3904 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
3905 [GCC_ANOC_BCR] = { 0x2e074, 0 },
3906 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
3907 [GCC_APSS_TCU_BCR] = { 0x12014, 0 },
3908 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3909 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3910 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
3911 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
3912 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
3913 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
3914 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
3915 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
3916 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3917 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
3918 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
3919 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
3920 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
3921 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
3922 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
3923 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
3924 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
3925 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
3926 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3927 [GCC_DCC_BCR] = { 0x35000, 0 },
3928 [GCC_DDRSS_BCR] = { 0x11000, 0 },
3929 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3930 [GCC_LPASS_BCR] = { 0x27000, 0 },
3931 [GCC_MDIO_BCR] = { 0x1703c, 0 },
3932 [GCC_MPM_BCR] = { 0x37000, 0 },
3933 [GCC_MSG_RAM_BCR] = { 0x26000, 0 },
3934 [GCC_NSS_BCR] = { 0x17000, 0 },
3935 [GCC_NSS_TBU_BCR] = { 0x12044, 0 },
3936 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
3937 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
3938 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
3939 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
3940 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
3941 [GCC_NSSCC_ARES] = { 0x17038, 8 },
3942 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
3943 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
3944 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
3945 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
3946 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
3947 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
3948 [GCC_NSS_CFG_ARES] = { 0x17038, 1 },
3949 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
3950 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
3951 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
3952 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
3953 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
3954 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
3955 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
3956 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3957 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
3958 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
3959 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
3960 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
3961 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
3962 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
3963 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
3964 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3965 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
3966 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
3967 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
3968 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
3969 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
3970 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
3971 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
3972 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3973 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
3974 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
3975 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
3976 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
3977 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
3978 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
3979 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
3980 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
3981 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
3982 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
3983 [GCC_PCIE0_BCR] = { 0x28000, 0 },
3984 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
3985 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
3986 [GCC_PCIE1_BCR] = { 0x29000, 0 },
3987 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
3988 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
3989 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
3990 [GCC_PCIE2_BCR] = { 0x2a000, 0 },
3991 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
3992 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
3993 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
3994 [GCC_PCIE3_BCR] = { 0x2b000, 0 },
3995 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
3996 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
3997 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
3998 [GCC_PCNOC_BCR] = { 0x31000, 0 },
3999 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4000 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4001 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4002 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4003 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4004 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4005 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4006 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4007 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4008 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4009 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4010 [GCC_PRNG_BCR] = { 0x13020, 0 },
4011 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4012 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4013 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4014 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4015 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4016 [GCC_QDSS_BCR] = { 0x2d000, 0 },
4017 [GCC_QPIC_BCR] = { 0x32000, 0 },
4018 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4019 [GCC_QPIC_ARES] = { 0x3201c, 0 },
4020 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4021 [GCC_RBCPR_BCR] = { 0x39000, 0 },
4022 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4023 [GCC_SDCC_BCR] = { 0x33000, 0 },
4024 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4025 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4026 [GCC_SNOC_BCR] = { 0x2e000, 0 },
4027 [GCC_SPDM_BCR] = { 0x36000, 0 },
4028 [GCC_TCSR_BCR] = { 0x3d000, 0 },
4029 [GCC_TLMM_BCR] = { 0x3e000, 0 },
4030 [GCC_TME_BCR] = { 0x10000, 0 },
4031 [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4032 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4033 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4034 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4035 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4036 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4037 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4038 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4039 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4040 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4041 [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4042 [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4043 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4044 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4045 [GCC_USB_BCR] = { 0x2c000, 0 },
4046 [GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4047 [GCC_WCSSAON_RESET] = { 0x25074, 0 },
4048 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4049 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4050 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4051 [GCC_WCSS_BCR] = { 0x18004, 0 },
4052 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4053 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4054 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4055 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4056 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4095 .max_register = 0x7fffc,