Lines Matching +full:0 +full:x29000
52 .offset = 0x21000,
55 .enable_reg = 0x0b000,
56 .enable_mask = BIT(0),
82 .offset = 0x21000,
95 .offset = 0x4a000,
98 .enable_reg = 0x0b000,
114 .offset = 0x4a000,
127 .offset = 0x24000,
130 .enable_reg = 0x0b000,
146 .offset = 0x24000,
159 .offset = 0x37000,
163 .enable_reg = 0x0b000,
179 .offset = 0x37000,
204 .offset = 0x25000,
208 .enable_reg = 0x0b000,
223 .offset = 0x25000,
237 .offset = 0x22000,
240 .enable_reg = 0x0b000,
255 .offset = 0x22000,
268 F(19200000, P_XO, 1, 0, 0),
269 F(50000000, P_GPLL0, 16, 0, 0),
270 F(100000000, P_GPLL0, 8, 0, 0),
281 { P_XO, 0 },
287 .cmd_rcgr = 0x27000,
314 .halt_reg = 0x30000,
316 .enable_reg = 0x30000,
332 F(19200000, P_XO, 1, 0, 0),
333 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
334 F(50000000, P_GPLL0, 16, 0, 0),
339 .cmd_rcgr = 0x0200c,
353 F(4800000, P_XO, 4, 0, 0),
354 F(9600000, P_XO, 2, 0, 0),
357 F(19200000, P_XO, 1, 0, 0),
359 F(50000000, P_GPLL0, 16, 0, 0),
364 .cmd_rcgr = 0x02024,
378 .cmd_rcgr = 0x03000,
391 .cmd_rcgr = 0x03014,
405 .cmd_rcgr = 0x04000,
418 .cmd_rcgr = 0x04014,
432 .cmd_rcgr = 0x05000,
445 .cmd_rcgr = 0x05014,
459 .cmd_rcgr = 0x06000,
472 .cmd_rcgr = 0x06014,
486 .cmd_rcgr = 0x07000,
499 .cmd_rcgr = 0x07014,
517 F(19200000, P_XO, 1, 0, 0),
533 .cmd_rcgr = 0x02044,
547 .cmd_rcgr = 0x03034,
561 .cmd_rcgr = 0x04034,
575 .cmd_rcgr = 0x05034,
589 .cmd_rcgr = 0x06034,
603 .cmd_rcgr = 0x07034,
622 { P_XO, 0 },
627 F(19200000, P_XO, 1, 0, 0),
628 F(200000000, P_GPLL0, 4, 0, 0),
633 .cmd_rcgr = 0x75054,
646 F(19200000, P_XO, 1, 0, 0),
657 { P_XO, 0 },
663 .cmd_rcgr = 0x75024,
682 { P_PCIE20_PHY0_PIPE, 0 },
687 .reg = 0x7501c,
703 .cmd_rcgr = 0x76054,
716 .cmd_rcgr = 0x76024,
735 { P_PCIE20_PHY1_PIPE, 0 },
740 .reg = 0x7601c,
760 F(96000000, P_GPLL2, 12, 0, 0),
761 F(177777778, P_GPLL0, 4.5, 0, 0),
762 F(192000000, P_GPLL2, 6, 0, 0),
763 F(384000000, P_GPLL2, 3, 0, 0),
775 { P_XO, 0 },
782 .cmd_rcgr = 0x42004,
796 F(19200000, P_XO, 1, 0, 0),
797 F(160000000, P_GPLL0, 5, 0, 0),
798 F(308570000, P_GPLL6, 3.5, 0, 0),
810 { P_XO, 0 },
817 .cmd_rcgr = 0x5d000,
831 .cmd_rcgr = 0x43004,
845 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
846 F(100000000, P_GPLL0, 8, 0, 0),
847 F(133330000, P_GPLL0, 6, 0, 0),
858 { P_XO, 0 },
864 .cmd_rcgr = 0x3e00c,
878 F(19200000, P_XO, 1, 0, 0),
883 .cmd_rcgr = 0x3e05c,
897 F(19200000, P_XO, 1, 0, 0),
911 { P_XO, 0 },
918 .cmd_rcgr = 0x3e020,
937 { P_USB3PHY_0_PIPE, 0 },
942 .reg = 0x3e048,
958 .cmd_rcgr = 0x3f00c,
972 .cmd_rcgr = 0x3f05c,
986 .cmd_rcgr = 0x3f020,
1005 { P_USB3PHY_1_PIPE, 0 },
1010 .reg = 0x3f048,
1026 .halt_reg = 0x30018,
1028 .enable_reg = 0x30018,
1057 F(19200000, P_XO, 1, 0, 0),
1058 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1059 F(100000000, P_GPLL0, 8, 0, 0),
1060 F(133333333, P_GPLL0, 6, 0, 0),
1061 F(160000000, P_GPLL0, 5, 0, 0),
1062 F(200000000, P_GPLL0, 4, 0, 0),
1063 F(266666667, P_GPLL0, 3, 0, 0),
1075 { P_XO, 0 },
1082 .cmd_rcgr = 0x26004,
1109 F(19200000, P_XO, 1, 0, 0),
1110 F(200000000, P_GPLL0, 4, 0, 0),
1115 .cmd_rcgr = 0x68098,
1128 F(19200000, P_XO, 1, 0, 0),
1129 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1141 { P_XO, 0 },
1148 .cmd_rcgr = 0x68088,
1174 F(19200000, P_XO, 1, 0, 0),
1175 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1186 { P_XO, 0 },
1192 .cmd_rcgr = 0x68144,
1206 F(19200000, P_XO, 1, 0, 0),
1207 F(187200000, P_UBI32_PLL, 8, 0, 0),
1208 F(748800000, P_UBI32_PLL, 2, 0, 0),
1209 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1210 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1224 { P_XO, 0 },
1233 .cmd_rcgr = 0x68104,
1247 .reg = 0x68118,
1248 .shift = 0,
1263 .cmd_rcgr = 0x68124,
1277 .reg = 0x68138,
1278 .shift = 0,
1293 F(19200000, P_XO, 1, 0, 0),
1294 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1304 { P_XO, 0 },
1309 .cmd_rcgr = 0x68090,
1322 F(19200000, P_XO, 1, 0, 0),
1323 F(400000000, P_GPLL0, 2, 0, 0),
1334 { P_XO, 0 },
1340 .cmd_rcgr = 0x68158,
1353 F(19200000, P_XO, 1, 0, 0),
1354 F(300000000, P_BIAS_PLL, 1, 0, 0),
1368 { P_XO, 0 },
1377 .cmd_rcgr = 0x68080,
1403 F(19200000, P_XO, 1, 0, 0),
1404 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1405 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1418 { P_XO, 0 },
1426 .cmd_rcgr = 0x68020,
1439 .reg = 0x68400,
1440 .shift = 0,
1455 F(19200000, P_XO, 1, 0, 0),
1456 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1457 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1470 { P_XO, 0 },
1478 .cmd_rcgr = 0x68028,
1491 .reg = 0x68404,
1492 .shift = 0,
1507 .cmd_rcgr = 0x68030,
1520 .reg = 0x68410,
1521 .shift = 0,
1536 .cmd_rcgr = 0x68038,
1549 .reg = 0x68414,
1550 .shift = 0,
1565 .cmd_rcgr = 0x68040,
1578 .reg = 0x68420,
1579 .shift = 0,
1594 .cmd_rcgr = 0x68048,
1607 .reg = 0x68424,
1608 .shift = 0,
1623 .cmd_rcgr = 0x68050,
1636 .reg = 0x68430,
1637 .shift = 0,
1652 .cmd_rcgr = 0x68058,
1665 .reg = 0x68434,
1666 .shift = 0,
1681 C(P_UNIPHY1_RX, 12.5, 0, 0),
1682 C(P_UNIPHY0_RX, 5, 0, 0),
1686 C(P_UNIPHY1_RX, 2.5, 0, 0),
1687 C(P_UNIPHY0_RX, 1, 0, 0),
1691 FMS(19200000, P_XO, 1, 0, 0),
1693 FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1695 FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1696 FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1712 { P_XO, 0 },
1722 .cmd_rcgr = 0x68060,
1735 .reg = 0x68440,
1736 .shift = 0,
1751 C(P_UNIPHY1_TX, 12.5, 0, 0),
1752 C(P_UNIPHY0_TX, 5, 0, 0),
1756 C(P_UNIPHY1_TX, 2.5, 0, 0),
1757 C(P_UNIPHY0_TX, 1, 0, 0),
1761 FMS(19200000, P_XO, 1, 0, 0),
1763 FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
1765 FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
1766 FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
1782 { P_XO, 0 },
1792 .cmd_rcgr = 0x68068,
1805 .reg = 0x68444,
1806 .shift = 0,
1821 C(P_UNIPHY2_RX, 5, 0, 0),
1822 C(P_UNIPHY2_RX, 12.5, 0, 0),
1826 C(P_UNIPHY2_RX, 1, 0, 0),
1827 C(P_UNIPHY2_RX, 2.5, 0, 0),
1831 FMS(19200000, P_XO, 1, 0, 0),
1833 FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
1835 FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
1836 FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
1849 { P_XO, 0 },
1857 .cmd_rcgr = 0x68070,
1870 .reg = 0x68450,
1871 .shift = 0,
1886 C(P_UNIPHY2_TX, 5, 0, 0),
1887 C(P_UNIPHY2_TX, 12.5, 0, 0),
1891 C(P_UNIPHY2_TX, 1, 0, 0),
1892 C(P_UNIPHY2_TX, 2.5, 0, 0),
1896 FMS(19200000, P_XO, 1, 0, 0),
1898 FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1900 FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1901 FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1914 { P_XO, 0 },
1922 .cmd_rcgr = 0x68078,
1935 .reg = 0x68454,
1936 .shift = 0,
1951 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1952 F(80000000, P_GPLL0, 10, 0, 0),
1953 F(100000000, P_GPLL0, 8, 0, 0),
1954 F(160000000, P_GPLL0, 5, 0, 0),
1959 .cmd_rcgr = 0x16004,
1972 F(19200000, P_XO, 1, 0, 0),
1985 { P_XO, 0 },
1993 .cmd_rcgr = 0x08004,
2007 .cmd_rcgr = 0x09004,
2021 .cmd_rcgr = 0x0a004,
2035 .halt_reg = 0x01008,
2037 .enable_reg = 0x01008,
2038 .enable_mask = BIT(0),
2051 .halt_reg = 0x02008,
2053 .enable_reg = 0x02008,
2054 .enable_mask = BIT(0),
2067 .halt_reg = 0x02004,
2069 .enable_reg = 0x02004,
2070 .enable_mask = BIT(0),
2083 .halt_reg = 0x03010,
2085 .enable_reg = 0x03010,
2086 .enable_mask = BIT(0),
2099 .halt_reg = 0x0300c,
2101 .enable_reg = 0x0300c,
2102 .enable_mask = BIT(0),
2115 .halt_reg = 0x04010,
2117 .enable_reg = 0x04010,
2118 .enable_mask = BIT(0),
2131 .halt_reg = 0x0400c,
2133 .enable_reg = 0x0400c,
2134 .enable_mask = BIT(0),
2147 .halt_reg = 0x05010,
2149 .enable_reg = 0x05010,
2150 .enable_mask = BIT(0),
2163 .halt_reg = 0x0500c,
2165 .enable_reg = 0x0500c,
2166 .enable_mask = BIT(0),
2179 .halt_reg = 0x06010,
2181 .enable_reg = 0x06010,
2182 .enable_mask = BIT(0),
2195 .halt_reg = 0x0600c,
2197 .enable_reg = 0x0600c,
2198 .enable_mask = BIT(0),
2211 .halt_reg = 0x07010,
2213 .enable_reg = 0x07010,
2214 .enable_mask = BIT(0),
2227 .halt_reg = 0x0700c,
2229 .enable_reg = 0x0700c,
2230 .enable_mask = BIT(0),
2243 .halt_reg = 0x0203c,
2245 .enable_reg = 0x0203c,
2246 .enable_mask = BIT(0),
2259 .halt_reg = 0x0302c,
2261 .enable_reg = 0x0302c,
2262 .enable_mask = BIT(0),
2275 .halt_reg = 0x0402c,
2277 .enable_reg = 0x0402c,
2278 .enable_mask = BIT(0),
2291 .halt_reg = 0x0502c,
2293 .enable_reg = 0x0502c,
2294 .enable_mask = BIT(0),
2307 .halt_reg = 0x0602c,
2309 .enable_reg = 0x0602c,
2310 .enable_mask = BIT(0),
2323 .halt_reg = 0x0702c,
2325 .enable_reg = 0x0702c,
2326 .enable_mask = BIT(0),
2339 .halt_reg = 0x13004,
2342 .enable_reg = 0x0b004,
2356 .halt_reg = 0x57024,
2358 .enable_reg = 0x57024,
2359 .enable_mask = BIT(0),
2372 .halt_reg = 0x57020,
2374 .enable_reg = 0x57020,
2375 .enable_mask = BIT(0),
2388 .halt_reg = 0x75010,
2390 .enable_reg = 0x75010,
2391 .enable_mask = BIT(0),
2404 .halt_reg = 0x75014,
2406 .enable_reg = 0x75014,
2407 .enable_mask = BIT(0),
2420 .halt_reg = 0x75008,
2422 .enable_reg = 0x75008,
2423 .enable_mask = BIT(0),
2436 .halt_reg = 0x7500c,
2438 .enable_reg = 0x7500c,
2439 .enable_mask = BIT(0),
2452 .halt_reg = 0x75018,
2455 .enable_reg = 0x75018,
2456 .enable_mask = BIT(0),
2469 .halt_reg = 0x26048,
2471 .enable_reg = 0x26048,
2472 .enable_mask = BIT(0),
2485 .halt_reg = 0x76010,
2487 .enable_reg = 0x76010,
2488 .enable_mask = BIT(0),
2501 .halt_reg = 0x76014,
2503 .enable_reg = 0x76014,
2504 .enable_mask = BIT(0),
2517 .halt_reg = 0x76008,
2519 .enable_reg = 0x76008,
2520 .enable_mask = BIT(0),
2533 .halt_reg = 0x7600c,
2535 .enable_reg = 0x7600c,
2536 .enable_mask = BIT(0),
2549 .halt_reg = 0x76018,
2552 .enable_reg = 0x76018,
2553 .enable_mask = BIT(0),
2566 .halt_reg = 0x2604c,
2568 .enable_reg = 0x2604c,
2569 .enable_mask = BIT(0),
2582 .halt_reg = 0x3e044,
2584 .enable_reg = 0x3e044,
2585 .enable_mask = BIT(0),
2598 .halt_reg = 0x26040,
2600 .enable_reg = 0x26040,
2601 .enable_mask = BIT(0),
2614 .halt_reg = 0x3e000,
2616 .enable_reg = 0x3e000,
2617 .enable_mask = BIT(0),
2630 .halt_reg = 0x3e008,
2632 .enable_reg = 0x3e008,
2633 .enable_mask = BIT(0),
2646 .halt_reg = 0x3e080,
2648 .enable_reg = 0x3e080,
2649 .enable_mask = BIT(0),
2662 .halt_reg = 0x3e040,
2665 .enable_reg = 0x3e040,
2666 .enable_mask = BIT(0),
2679 .halt_reg = 0x3e004,
2681 .enable_reg = 0x3e004,
2682 .enable_mask = BIT(0),
2695 .halt_reg = 0x3f044,
2697 .enable_reg = 0x3f044,
2698 .enable_mask = BIT(0),
2711 .halt_reg = 0x26044,
2713 .enable_reg = 0x26044,
2714 .enable_mask = BIT(0),
2727 .halt_reg = 0x3f000,
2729 .enable_reg = 0x3f000,
2730 .enable_mask = BIT(0),
2743 .halt_reg = 0x3f008,
2745 .enable_reg = 0x3f008,
2746 .enable_mask = BIT(0),
2759 .halt_reg = 0x3f080,
2761 .enable_reg = 0x3f080,
2762 .enable_mask = BIT(0),
2775 .halt_reg = 0x3f040,
2778 .enable_reg = 0x3f040,
2779 .enable_mask = BIT(0),
2792 .halt_reg = 0x3f004,
2794 .enable_reg = 0x3f004,
2795 .enable_mask = BIT(0),
2808 .halt_reg = 0x4201c,
2810 .enable_reg = 0x4201c,
2811 .enable_mask = BIT(0),
2824 .halt_reg = 0x42018,
2826 .enable_reg = 0x42018,
2827 .enable_mask = BIT(0),
2840 .halt_reg = 0x5d014,
2842 .enable_reg = 0x5d014,
2843 .enable_mask = BIT(0),
2856 .halt_reg = 0x4301c,
2858 .enable_reg = 0x4301c,
2859 .enable_mask = BIT(0),
2872 .halt_reg = 0x43018,
2874 .enable_reg = 0x43018,
2875 .enable_mask = BIT(0),
2888 .halt_reg = 0x1d03c,
2890 .enable_reg = 0x1d03c,
2891 .enable_mask = BIT(0),
2904 .halt_reg = 0x68174,
2906 .enable_reg = 0x68174,
2907 .enable_mask = BIT(0),
2920 .halt_reg = 0x68170,
2922 .enable_reg = 0x68170,
2923 .enable_mask = BIT(0),
2936 .halt_reg = 0x68160,
2938 .enable_reg = 0x68160,
2939 .enable_mask = BIT(0),
2952 .halt_reg = 0x68164,
2954 .enable_reg = 0x68164,
2955 .enable_mask = BIT(0),
2968 .halt_reg = 0x68318,
2970 .enable_reg = 0x68318,
2971 .enable_mask = BIT(0),
2984 .halt_reg = 0x6819c,
2986 .enable_reg = 0x6819c,
2987 .enable_mask = BIT(0),
3000 .halt_reg = 0x68198,
3002 .enable_reg = 0x68198,
3003 .enable_mask = BIT(0),
3016 .halt_reg = 0x68178,
3018 .enable_reg = 0x68178,
3019 .enable_mask = BIT(0),
3032 .halt_reg = 0x68168,
3034 .enable_reg = 0x68168,
3035 .enable_mask = BIT(0),
3048 .halt_reg = 0x6833c,
3050 .enable_reg = 0x6833c,
3051 .enable_mask = BIT(0),
3064 .halt_reg = 0x68194,
3066 .enable_reg = 0x68194,
3067 .enable_mask = BIT(0),
3080 .halt_reg = 0x68190,
3082 .enable_reg = 0x68190,
3083 .enable_mask = BIT(0),
3096 .halt_reg = 0x68338,
3098 .enable_reg = 0x68338,
3099 .enable_mask = BIT(0),
3112 .halt_reg = 0x6816c,
3114 .enable_reg = 0x6816c,
3115 .enable_mask = BIT(0),
3128 .halt_reg = 0x68310,
3131 .enable_reg = 0x68310,
3132 .enable_mask = BIT(0),
3145 .halt_reg = 0x6830c,
3147 .enable_reg = 0x6830c,
3148 .enable_mask = BIT(0),
3161 .halt_reg = 0x68308,
3163 .enable_reg = 0x68308,
3164 .enable_mask = BIT(0),
3177 .halt_reg = 0x68314,
3179 .enable_reg = 0x68314,
3180 .enable_mask = BIT(0),
3193 .halt_reg = 0x68304,
3195 .enable_reg = 0x68304,
3196 .enable_mask = BIT(0),
3209 .halt_reg = 0x68300,
3211 .enable_reg = 0x68300,
3212 .enable_mask = BIT(0),
3225 .halt_reg = 0x68180,
3227 .enable_reg = 0x68180,
3228 .enable_mask = BIT(0),
3241 .halt_reg = 0x68188,
3243 .enable_reg = 0x68188,
3244 .enable_mask = BIT(0),
3257 .halt_reg = 0x68184,
3259 .enable_reg = 0x68184,
3260 .enable_mask = BIT(0),
3273 .halt_reg = 0x68270,
3275 .enable_reg = 0x68270,
3276 .enable_mask = BIT(0),
3289 .halt_reg = 0x68274,
3291 .enable_reg = 0x68274,
3292 .enable_mask = BIT(0),
3305 .halt_reg = 0x6820c,
3308 .enable_reg = 0x6820c,
3309 .enable_mask = BIT(0),
3322 .halt_reg = 0x68200,
3325 .enable_reg = 0x68200,
3326 .enable_mask = BIT(0),
3339 .halt_reg = 0x68204,
3342 .enable_reg = 0x68204,
3343 .enable_mask = BIT(0),
3356 .halt_reg = 0x68210,
3359 .enable_reg = 0x68210,
3360 .enable_mask = BIT(0),
3373 .halt_reg = 0x68208,
3376 .enable_reg = 0x68208,
3377 .enable_mask = BIT(0),
3390 .halt_reg = 0x6822c,
3393 .enable_reg = 0x6822c,
3394 .enable_mask = BIT(0),
3407 .halt_reg = 0x68220,
3410 .enable_reg = 0x68220,
3411 .enable_mask = BIT(0),
3424 .halt_reg = 0x68224,
3427 .enable_reg = 0x68224,
3428 .enable_mask = BIT(0),
3441 .halt_reg = 0x68230,
3444 .enable_reg = 0x68230,
3445 .enable_mask = BIT(0),
3458 .halt_reg = 0x68228,
3461 .enable_reg = 0x68228,
3462 .enable_mask = BIT(0),
3475 .halt_reg = 0x56308,
3477 .enable_reg = 0x56308,
3478 .enable_mask = BIT(0),
3491 .halt_reg = 0x5630c,
3493 .enable_reg = 0x5630c,
3494 .enable_mask = BIT(0),
3507 .halt_reg = 0x58004,
3509 .enable_reg = 0x58004,
3510 .enable_mask = BIT(0),
3523 .halt_reg = 0x56008,
3525 .enable_reg = 0x56008,
3526 .enable_mask = BIT(0),
3539 .halt_reg = 0x5600c,
3541 .enable_reg = 0x5600c,
3542 .enable_mask = BIT(0),
3555 .halt_reg = 0x56108,
3557 .enable_reg = 0x56108,
3558 .enable_mask = BIT(0),
3571 .halt_reg = 0x5610c,
3573 .enable_reg = 0x5610c,
3574 .enable_mask = BIT(0),
3587 .halt_reg = 0x56208,
3589 .enable_reg = 0x56208,
3590 .enable_mask = BIT(0),
3603 .halt_reg = 0x5620c,
3605 .enable_reg = 0x5620c,
3606 .enable_mask = BIT(0),
3619 .halt_reg = 0x68240,
3621 .enable_reg = 0x68240,
3622 .enable_mask = BIT(0),
3635 .halt_reg = 0x68244,
3637 .enable_reg = 0x68244,
3638 .enable_mask = BIT(0),
3651 .halt_reg = 0x68248,
3653 .enable_reg = 0x68248,
3654 .enable_mask = BIT(0),
3667 .halt_reg = 0x6824c,
3669 .enable_reg = 0x6824c,
3670 .enable_mask = BIT(0),
3683 .halt_reg = 0x68250,
3685 .enable_reg = 0x68250,
3686 .enable_mask = BIT(0),
3699 .halt_reg = 0x68254,
3701 .enable_reg = 0x68254,
3702 .enable_mask = BIT(0),
3715 .halt_reg = 0x68258,
3717 .enable_reg = 0x68258,
3718 .enable_mask = BIT(0),
3731 .halt_reg = 0x6825c,
3733 .enable_reg = 0x6825c,
3734 .enable_mask = BIT(0),
3747 .halt_reg = 0x68260,
3749 .enable_reg = 0x68260,
3750 .enable_mask = BIT(0),
3763 .halt_reg = 0x68264,
3765 .enable_reg = 0x68264,
3766 .enable_mask = BIT(0),
3779 .halt_reg = 0x68268,
3781 .enable_reg = 0x68268,
3782 .enable_mask = BIT(0),
3795 .halt_reg = 0x6826c,
3797 .enable_reg = 0x6826c,
3798 .enable_mask = BIT(0),
3811 .halt_reg = 0x68320,
3813 .enable_reg = 0x68320,
3814 .enable_mask = BIT(0),
3827 .halt_reg = 0x68324,
3829 .enable_reg = 0x68324,
3830 .enable_mask = BIT(0),
3843 .halt_reg = 0x68328,
3845 .enable_reg = 0x68328,
3846 .enable_mask = BIT(0),
3859 .halt_reg = 0x6832c,
3861 .enable_reg = 0x6832c,
3862 .enable_mask = BIT(0),
3875 .halt_reg = 0x68330,
3877 .enable_reg = 0x68330,
3878 .enable_mask = BIT(0),
3891 .halt_reg = 0x68334,
3893 .enable_reg = 0x68334,
3894 .enable_mask = BIT(0),
3907 .halt_reg = 0x56010,
3909 .enable_reg = 0x56010,
3910 .enable_mask = BIT(0),
3923 .halt_reg = 0x56014,
3925 .enable_reg = 0x56014,
3926 .enable_mask = BIT(0),
3939 .halt_reg = 0x56018,
3941 .enable_reg = 0x56018,
3942 .enable_mask = BIT(0),
3955 .halt_reg = 0x5601c,
3957 .enable_reg = 0x5601c,
3958 .enable_mask = BIT(0),
3971 .halt_reg = 0x56020,
3973 .enable_reg = 0x56020,
3974 .enable_mask = BIT(0),
3987 .halt_reg = 0x56024,
3989 .enable_reg = 0x56024,
3990 .enable_mask = BIT(0),
4003 .halt_reg = 0x56028,
4005 .enable_reg = 0x56028,
4006 .enable_mask = BIT(0),
4019 .halt_reg = 0x5602c,
4021 .enable_reg = 0x5602c,
4022 .enable_mask = BIT(0),
4035 .halt_reg = 0x56030,
4037 .enable_reg = 0x56030,
4038 .enable_mask = BIT(0),
4051 .halt_reg = 0x56034,
4053 .enable_reg = 0x56034,
4054 .enable_mask = BIT(0),
4067 .halt_reg = 0x56110,
4069 .enable_reg = 0x56110,
4070 .enable_mask = BIT(0),
4083 .halt_reg = 0x56114,
4085 .enable_reg = 0x56114,
4086 .enable_mask = BIT(0),
4099 .halt_reg = 0x56210,
4101 .enable_reg = 0x56210,
4102 .enable_mask = BIT(0),
4115 .halt_reg = 0x56214,
4117 .enable_reg = 0x56214,
4118 .enable_mask = BIT(0),
4131 .halt_reg = 0x16024,
4134 .enable_reg = 0x0b004,
4135 .enable_mask = BIT(0),
4148 .halt_reg = 0x16020,
4151 .enable_reg = 0x0b004,
4165 .halt_reg = 0x1601c,
4168 .enable_reg = 0x0b004,
4182 .halt_reg = 0x08000,
4184 .enable_reg = 0x08000,
4185 .enable_mask = BIT(0),
4198 .halt_reg = 0x09000,
4200 .enable_reg = 0x09000,
4201 .enable_mask = BIT(0),
4214 .halt_reg = 0x0a000,
4216 .enable_reg = 0x0a000,
4217 .enable_mask = BIT(0),
4230 F(19200000, P_XO, 1, 0, 0),
4231 F(100000000, P_GPLL0, 8, 0, 0),
4236 .cmd_rcgr = 0x75070,
4249 .halt_reg = 0x75070,
4252 .enable_reg = 0x75070,
4267 .halt_reg = 0x75048,
4270 .enable_reg = 0x75048,
4271 .enable_mask = BIT(0),
4285 .gdscr = 0x3e078,
4293 .gdscr = 0x3f078,
4301 .l = 0x4e,
4302 .config_ctl_val = 0x200d4aa8,
4303 .config_ctl_hi_val = 0x3c2,
4304 .main_output_mask = BIT(0),
4306 .pre_div_val = 0x0,
4308 .post_div_val = 0x0,
4313 .l = 0x3e,
4314 .alpha = 0x0,
4315 .alpha_hi = 0x80,
4316 .config_ctl_val = 0x4001055b,
4317 .main_output_mask = BIT(0),
4318 .pre_div_val = 0x0,
4320 .post_div_val = 0x1 << 8,
4323 .vco_val = 0x0,
4569 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4570 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4571 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4572 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4573 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4574 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4575 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4576 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4577 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4578 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4579 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4580 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4581 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4582 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4583 [GCC_SMMU_BCR] = { 0x12000, 0 },
4584 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4585 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4586 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4587 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4588 [GCC_PRNG_BCR] = { 0x13000, 0 },
4589 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4590 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4591 [GCC_WCSS_BCR] = { 0x18000, 0 },
4592 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4593 [GCC_NSS_BCR] = { 0x19000, 0 },
4594 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4595 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4596 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4597 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4598 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4599 [GCC_TCSR_BCR] = { 0x28000, 0 },
4600 [GCC_QDSS_BCR] = { 0x29000, 0 },
4601 [GCC_DCD_BCR] = { 0x2a000, 0 },
4602 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4603 [GCC_MPM_BCR] = { 0x2c000, 0 },
4604 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4605 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4606 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4607 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4608 [GCC_TLMM_BCR] = { 0x34000, 0 },
4609 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4610 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4611 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4612 [GCC_USB0_BCR] = { 0x3e070, 0 },
4613 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4614 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4615 [GCC_USB1_BCR] = { 0x3f070, 0 },
4616 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4617 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4618 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4619 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4620 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4621 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4622 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4623 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4624 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4625 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4626 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4627 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4628 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4629 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4630 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4631 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4632 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4633 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4634 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4635 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4636 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4637 [GCC_QPIC_BCR] = { 0x57018, 0 },
4638 [GCC_MDIO_BCR] = { 0x58000, 0 },
4639 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4640 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4641 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4642 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4643 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4644 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4645 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4646 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4647 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4648 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4649 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4650 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4651 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4652 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4653 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4654 [GCC_DCC_BCR] = { 0x77000, 0 },
4655 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4656 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4657 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4658 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4659 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4660 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4661 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4662 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4663 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4664 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4665 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4666 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4667 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4668 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4669 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4670 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4671 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4672 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4673 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4674 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4675 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4676 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4677 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4678 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4679 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4680 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4681 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4682 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4683 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4684 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4685 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4686 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4687 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4688 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4689 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4690 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4691 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4692 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4693 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4694 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4695 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4696 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4697 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4698 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4699 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4700 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4701 [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
4702 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4703 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4704 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4705 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4706 [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4707 [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
4708 [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
4709 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4710 [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
4711 [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
4712 [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
4713 [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
4714 [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
4732 .max_register = 0x7fffc,
4757 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq8074_probe()