Lines Matching +full:0 +full:x29000
55 .offset = 0x20000,
58 .enable_reg = 0xb000,
59 .enable_mask = BIT(0),
83 .offset = 0x21000,
86 .enable_reg = 0xb000,
98 { 0x1, 2 },
103 .offset = 0x21000,
118 .offset = 0x22000,
121 .enable_reg = 0xb000,
144 { P_XO, 0 },
148 { P_XO, 0 },
160 { P_XO, 0 },
170 { P_XO, 0 },
182 { P_XO, 0 },
196 { P_XO, 0 },
204 { P_XO, 0 },
226 { P_XO, 0 },
240 { P_XO, 0 },
254 { P_XO, 0 },
268 { P_XO, 0 },
280 { P_XO, 0 },
292 F(24000000, P_XO, 1, 0, 0),
293 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
298 .cmd_rcgr = 0x1c004,
299 .mnd_width = 0,
312 F(24000000, P_XO, 1, 0, 0),
317 .cmd_rcgr = 0x34004,
318 .mnd_width = 0,
331 .halt_reg = 0x34018,
334 .enable_reg = 0x34018,
335 .enable_mask = BIT(0),
363 .cmd_rcgr = 0x17088,
364 .mnd_width = 0,
377 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
382 .cmd_rcgr = 0x28018,
383 .mnd_width = 0,
396 .cmd_rcgr = 0x28020,
397 .mnd_width = 0,
410 .cmd_rcgr = 0x29018,
411 .mnd_width = 0,
424 .cmd_rcgr = 0x29020,
425 .mnd_width = 0,
438 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
443 .cmd_rcgr = 0x2a018,
444 .mnd_width = 0,
457 .cmd_rcgr = 0x2a020,
458 .mnd_width = 0,
471 .cmd_rcgr = 0x2b018,
472 .mnd_width = 0,
485 .cmd_rcgr = 0x2b020,
486 .mnd_width = 0,
504 .cmd_rcgr = 0x28004,
518 F(4800000, P_XO, 5, 0, 0),
519 F(9600000, P_XO, 2.5, 0, 0),
520 F(24000000, P_XO, 1, 0, 0),
521 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
522 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
527 .cmd_rcgr = 0x2018,
528 .mnd_width = 0,
541 .cmd_rcgr = 0x3018,
542 .mnd_width = 0,
556 F(4800000, P_XO, 5, 0, 0),
559 F(24000000, P_XO, 1, 0, 0),
562 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
567 .cmd_rcgr = 0x4004,
581 .cmd_rcgr = 0x5004,
596 F(4800000, P_XO, 5, 0, 0),
599 F(24000000, P_XO, 1, 0, 0),
601 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
602 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
607 .cmd_rcgr = 0x202c,
621 .cmd_rcgr = 0x302c,
637 F(24000000, P_XO, 1, 0, 0),
640 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
641 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
642 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
647 .cmd_rcgr = 0x33004,
661 F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
666 .cmd_rcgr = 0x33018,
680 .cmd_rcgr = 0x17090,
681 .mnd_width = 0,
694 .cmd_rcgr = 0x2c018,
708 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
713 .cmd_rcgr = 0x2c004,
727 F(24000000, P_XO, 1, 0, 0),
733 .cmd_rcgr = 0x2c02c,
747 .cmd_rcgr = 0x3c004,
761 F(24000000, P_XO, 1, 0, 0),
762 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
767 .cmd_rcgr = 0x25030,
780 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
785 .cmd_rcgr = 0x2d004,
798 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
803 .cmd_rcgr = 0x2d01c,
843 F(24000000, P_XO, 1, 0, 0),
844 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
845 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
846 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
851 .cmd_rcgr = 0x2e004,
864 F(24000000, P_XO, 1, 0, 0),
865 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
866 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
871 .cmd_rcgr = 0x31004,
872 .mnd_width = 0,
885 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
890 .cmd_rcgr = 0x27004,
891 .mnd_width = 0,
904 .cmd_rcgr = 0x2700c,
905 .mnd_width = 0,
931 F(32000, P_SLEEP_CLK, 1, 0, 0),
936 .cmd_rcgr = 0x3400c,
937 .mnd_width = 0,
950 F(24000000, P_XO, 1, 0, 0),
951 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
952 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
953 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
954 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
959 .cmd_rcgr = 0x32004,
960 .mnd_width = 0,
973 .cmd_rcgr = 0x32020,
974 .mnd_width = 0,
987 .cmd_rcgr = 0x28028,
988 .mnd_width = 0,
1001 .cmd_rcgr = 0x29028,
1002 .mnd_width = 0,
1015 .cmd_rcgr = 0x2a028,
1016 .mnd_width = 0,
1029 .cmd_rcgr = 0x2b028,
1030 .mnd_width = 0,
1043 .reg = 0x2020,
1044 .shift = 0,
1058 .reg = 0x3020,
1059 .shift = 0,
1073 .reg = 0x2c040,
1074 .shift = 0,
1088 .reg = 0x3c018,
1089 .shift = 0,
1103 .halt_reg = 0x1c00c,
1106 .enable_reg = 0x1c00c,
1107 .enable_mask = BIT(0),
1121 .halt_reg = 0x31088,
1124 .enable_reg = 0x31088,
1125 .enable_mask = BIT(0),
1139 .halt_reg = 0x3108c,
1142 .enable_reg = 0x3108c,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x31090,
1160 .enable_reg = 0x31090,
1161 .enable_mask = BIT(0),
1175 .halt_reg = 0x31094,
1178 .enable_reg = 0x31094,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0x310a8,
1196 .enable_reg = 0x310a8,
1197 .enable_mask = BIT(0),
1211 .halt_reg = 0x17040,
1214 .enable_reg = 0x17040,
1215 .enable_mask = BIT(0),
1229 .halt_reg = 0x17018,
1232 .enable_reg = 0x17018,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x17034,
1250 .enable_reg = 0x17034,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x1702c,
1268 .enable_reg = 0x1702c,
1269 .enable_mask = BIT(0),
1283 .halt_reg = 0x17014,
1286 .enable_reg = 0x17014,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0x17030,
1304 .enable_reg = 0x17030,
1305 .enable_mask = BIT(0),
1319 .halt_reg = 0x17080,
1322 .enable_reg = 0x17080,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x1701c,
1340 .enable_reg = 0x1701c,
1341 .enable_mask = BIT(0),
1355 .halt_reg = 0x1707c,
1358 .enable_reg = 0x1707c,
1359 .enable_mask = BIT(0),
1373 .halt_reg = 0x17028,
1376 .enable_reg = 0x17028,
1377 .enable_mask = BIT(0),
1391 .halt_reg = 0x17020,
1394 .enable_reg = 0x17020,
1395 .enable_mask = BIT(0),
1409 .halt_reg = 0x17074,
1412 .enable_reg = 0x17074,
1413 .enable_mask = BIT(0),
1427 .halt_reg = 0x28030,
1430 .enable_reg = 0x28030,
1431 .enable_mask = BIT(0),
1445 .halt_reg = 0x28070,
1448 .enable_reg = 0x28070,
1449 .enable_mask = BIT(0),
1463 .halt_reg = 0x28038,
1466 .enable_reg = 0x28038,
1467 .enable_mask = BIT(0),
1481 .halt_reg = 0x2e07c,
1484 .enable_reg = 0x2e07c,
1485 .enable_mask = BIT(0),
1499 .halt_reg = 0x28048,
1502 .enable_reg = 0x28048,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x28040,
1520 .enable_reg = 0x28040,
1521 .enable_mask = BIT(0),
1535 .reg = 0x28064,
1549 .halt_reg = 0x28068,
1552 .enable_reg = 0x28068,
1553 .enable_mask = BIT(0),
1567 .halt_reg = 0x29030,
1570 .enable_reg = 0x29030,
1571 .enable_mask = BIT(0),
1585 .halt_reg = 0x29074,
1588 .enable_reg = 0x29074,
1589 .enable_mask = BIT(0),
1603 .halt_reg = 0x29038,
1606 .enable_reg = 0x29038,
1607 .enable_mask = BIT(0),
1621 .halt_reg = 0x2e084,
1624 .enable_reg = 0x2e084,
1625 .enable_mask = BIT(0),
1639 .halt_reg = 0x29048,
1642 .enable_reg = 0x29048,
1643 .enable_mask = BIT(0),
1657 .halt_reg = 0x29040,
1660 .enable_reg = 0x29040,
1661 .enable_mask = BIT(0),
1675 .reg = 0x29064,
1689 .halt_reg = 0x29068,
1692 .enable_reg = 0x29068,
1693 .enable_mask = BIT(0),
1708 .halt_reg = 0x2a030,
1711 .enable_reg = 0x2a030,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x2a078,
1729 .enable_reg = 0x2a078,
1730 .enable_mask = BIT(0),
1744 .halt_reg = 0x2a038,
1747 .enable_reg = 0x2a038,
1748 .enable_mask = BIT(0),
1762 .halt_reg = 0x2e080,
1765 .enable_reg = 0x2e080,
1766 .enable_mask = BIT(0),
1780 .halt_reg = 0x2a048,
1783 .enable_reg = 0x2a048,
1784 .enable_mask = BIT(0),
1798 .halt_reg = 0x2a040,
1801 .enable_reg = 0x2a040,
1802 .enable_mask = BIT(0),
1816 .reg = 0x2a064,
1830 .halt_reg = 0x2a068,
1833 .enable_reg = 0x2a068,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x2b030,
1851 .enable_reg = 0x2b030,
1852 .enable_mask = BIT(0),
1866 .halt_reg = 0x2b07c,
1869 .enable_reg = 0x2b07c,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x2b038,
1887 .enable_reg = 0x2b038,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x2e090,
1905 .enable_reg = 0x2e090,
1906 .enable_mask = BIT(0),
1920 .halt_reg = 0x2b048,
1923 .enable_reg = 0x2b048,
1924 .enable_mask = BIT(0),
1938 .halt_reg = 0x2b040,
1941 .enable_reg = 0x2b040,
1942 .enable_mask = BIT(0),
1956 .reg = 0x2b064,
1970 .halt_reg = 0x2b068,
1973 .enable_reg = 0x2b068,
1974 .enable_mask = BIT(0),
1988 .halt_reg = 0x13024,
1991 .enable_reg = 0xb004,
2006 .halt_reg = 0x1014,
2009 .enable_reg = 0xb004,
2024 .halt_reg = 0x102c,
2027 .enable_reg = 0xb004,
2042 .halt_reg = 0x2024,
2045 .enable_reg = 0x2024,
2046 .enable_mask = BIT(0),
2060 .halt_reg = 0x3024,
2063 .enable_reg = 0x3024,
2064 .enable_mask = BIT(0),
2078 .halt_reg = 0x4020,
2081 .enable_reg = 0x4020,
2082 .enable_mask = BIT(0),
2096 .halt_reg = 0x5020,
2099 .enable_reg = 0x5020,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x2040,
2117 .enable_reg = 0x2040,
2118 .enable_mask = BIT(0),
2132 .halt_reg = 0x3040,
2135 .enable_reg = 0x3040,
2136 .enable_mask = BIT(0),
2150 .halt_reg = 0x3303c,
2153 .enable_reg = 0x3303c,
2154 .enable_mask = BIT(0),
2168 .halt_reg = 0x3302c,
2171 .enable_reg = 0x3302c,
2172 .enable_mask = BIT(0),
2186 .halt_reg = 0x33034,
2189 .enable_reg = 0x33034,
2190 .enable_mask = BIT(0),
2204 .halt_reg = 0x1704c,
2207 .enable_reg = 0x1704c,
2208 .enable_mask = BIT(0),
2222 .halt_reg = 0x17048,
2225 .enable_reg = 0x17048,
2226 .enable_mask = BIT(0),
2240 .halt_reg = 0x1705c,
2243 .enable_reg = 0x1705c,
2244 .enable_mask = BIT(0),
2258 .halt_reg = 0x17058,
2261 .enable_reg = 0x17058,
2262 .enable_mask = BIT(0),
2276 .halt_reg = 0x1706c,
2279 .enable_reg = 0x1706c,
2280 .enable_mask = BIT(0),
2294 .halt_reg = 0x17068,
2297 .enable_reg = 0x17068,
2298 .enable_mask = BIT(0),
2312 .halt_reg = 0x2c04c,
2315 .enable_reg = 0x2c04c,
2316 .enable_mask = BIT(0),
2330 .halt_reg = 0x2c044,
2333 .enable_reg = 0x2c044,
2334 .enable_mask = BIT(0),
2348 .halt_reg = 0x2c050,
2351 .enable_reg = 0x2c050,
2352 .enable_mask = BIT(0),
2366 .halt_reg = 0x3c024,
2369 .enable_reg = 0x3c024,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x2c05c,
2387 .enable_reg = 0x2c05c,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0x3c01c,
2405 .enable_reg = 0x3c01c,
2406 .enable_mask = BIT(0),
2420 .halt_reg = 0x3c028,
2423 .enable_reg = 0x3c028,
2424 .enable_mask = BIT(0),
2438 .reg = 0x2c074,
2452 .halt_reg = 0x2c054,
2455 .enable_reg = 0x2c054,
2456 .enable_mask = BIT(0),
2470 .halt_reg = 0x2c058,
2473 .enable_reg = 0x2c058,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x3c020,
2491 .enable_reg = 0x3c020,
2492 .enable_mask = BIT(0),
2506 .halt_reg = 0x3a004,
2509 .enable_reg = 0x3a004,
2510 .enable_mask = BIT(0),
2524 .halt_reg = 0x3a008,
2527 .enable_reg = 0x3a008,
2528 .enable_mask = BIT(0),
2542 .halt_reg = 0x27014,
2545 .enable_reg = 0x27014,
2546 .enable_mask = BIT(0),
2560 .halt_reg = 0x2e028,
2563 .enable_reg = 0x2e028,
2564 .enable_mask = BIT(0),
2578 .halt_reg = 0x27018,
2581 .enable_reg = 0x27018,
2582 .enable_mask = BIT(0),
2596 .halt_reg = 0x31020,
2599 .enable_reg = 0x31020,
2600 .enable_mask = BIT(0),
2614 .halt_reg = 0x30004,
2617 .enable_reg = 0x30004,
2618 .enable_mask = BIT(0),
2632 .halt_reg = 0x32010,
2635 .enable_reg = 0x32010,
2636 .enable_mask = BIT(0),
2650 .halt_reg = 0x32028,
2653 .enable_reg = 0x32028,
2654 .enable_mask = BIT(0),
2668 .halt_reg = 0x3200c,
2671 .enable_reg = 0x3200c,
2672 .enable_mask = BIT(0),
2686 .halt_reg = 0x2d058,
2688 .enable_reg = 0x2d058,
2689 .enable_mask = BIT(0),
2703 .halt_reg = 0x2d034,
2705 .enable_reg = 0x2d034,
2706 .enable_mask = BIT(0),
2720 .halt_reg = 0x28028,
2722 .enable_reg = 0x28028,
2737 .halt_reg = 0x29028,
2739 .enable_reg = 0x29028,
2754 .halt_reg = 0x2a028,
2756 .enable_reg = 0x2a028,
2771 .halt_reg = 0x2b028,
2773 .enable_reg = 0x2b028,
2934 [GCC_QUPV3_BCR] = { 0x01000, 0 },
2935 [GCC_QUPV3_I2C0_BCR] = { 0x02000, 0 },
2936 [GCC_QUPV3_UART0_BCR] = { 0x02020, 0 },
2937 [GCC_QUPV3_I2C1_BCR] = { 0x03000, 0 },
2938 [GCC_QUPV3_UART1_BCR] = { 0x03028, 0 },
2939 [GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 },
2940 [GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 },
2941 [GCC_IMEM_BCR] = { 0x0e000, 0 },
2942 [GCC_TME_BCR] = { 0x100000, 0 },
2943 [GCC_DDRSS_BCR] = { 0x11000, 0 },
2944 [GCC_PRNG_BCR] = { 0x13020, 0 },
2945 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
2946 [GCC_NSS_BCR] = { 0x17000, 0 },
2947 [GCC_MDIO_BCR] = { 0x1703c, 0 },
2948 [GCC_UNIPHY0_BCR] = { 0x17044, 0 },
2949 [GCC_UNIPHY1_BCR] = { 0x17054, 0 },
2950 [GCC_UNIPHY2_BCR] = { 0x17064, 0 },
2951 [GCC_WCSS_BCR] = { 0x18004, 0 },
2952 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
2953 [GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 },
2954 [GCC_ADSS_BCR] = { 0x1c000, 0 },
2955 [GCC_LPASS_BCR] = { 0x27000, 0 },
2956 [GCC_PCIE0_BCR] = { 0x28000, 0 },
2957 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
2958 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
2959 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
2960 [GCC_PCIE1_BCR] = { 0x29000, 0 },
2961 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
2962 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
2963 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
2964 [GCC_PCIE2_BCR] = { 0x2a000, 0 },
2965 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
2966 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
2967 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
2968 [GCC_PCIE3_BCR] = { 0x2b000, 0 },
2969 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
2970 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
2971 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
2972 [GCC_USB_BCR] = { 0x2c000, 0 },
2973 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
2974 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
2975 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
2976 [GCC_QDSS_BCR] = { 0x2d000, 0 },
2977 [GCC_SNOC_BCR] = { 0x2e000, 0 },
2978 [GCC_ANOC_BCR] = { 0x2e074, 0 },
2979 [GCC_PCNOC_BCR] = { 0x31000, 0 },
2980 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
2981 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
2982 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
2983 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
2984 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
2985 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
2986 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
2987 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
2988 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
2989 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
2990 [GCC_QPIC_BCR] = { 0x32000, 0 },
2991 [GCC_SDCC_BCR] = { 0x33000, 0 },
2992 [GCC_DCC_BCR] = { 0x35000, 0 },
2993 [GCC_SPDM_BCR] = { 0x36000, 0 },
2994 [GCC_MPM_BCR] = { 0x37000, 0 },
2995 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
2996 [GCC_RBCPR_BCR] = { 0x39000, 0 },
2997 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
2998 [GCC_TCSR_BCR] = { 0x3d000, 0 },
2999 [GCC_TLMM_BCR] = { 0x3e000, 0 },
3000 [GCC_QUPV3_AHB_MST_ARES] = { 0x01014, 2 },
3001 [GCC_QUPV3_CORE_ARES] = { 0x01018, 2 },
3002 [GCC_QUPV3_2X_CORE_ARES] = { 0x01020, 2 },
3003 [GCC_QUPV3_SLEEP_ARES] = { 0x01028, 2 },
3004 [GCC_QUPV3_AHB_SLV_ARES] = { 0x0102c, 2 },
3005 [GCC_QUPV3_I2C0_ARES] = { 0x02024, 2 },
3006 [GCC_QUPV3_UART0_ARES] = { 0x02040, 2 },
3007 [GCC_QUPV3_I2C1_ARES] = { 0x03024, 2 },
3008 [GCC_QUPV3_UART1_ARES] = { 0x03040, 2 },
3009 [GCC_QUPV3_SPI0_ARES] = { 0x04020, 2 },
3010 [GCC_QUPV3_SPI1_ARES] = { 0x05020, 2 },
3011 [GCC_DEBUG_ARES] = { 0x06068, 2 },
3012 [GCC_GP1_ARES] = { 0x08018, 2 },
3013 [GCC_GP2_ARES] = { 0x09018, 2 },
3014 [GCC_GP3_ARES] = { 0x0a018, 2 },
3015 [GCC_IMEM_AXI_ARES] = { 0x0e004, 2 },
3016 [GCC_IMEM_CFG_AHB_ARES] = { 0x0e00c, 2 },
3017 [GCC_TME_ARES] = { 0x100b4, 2 },
3018 [GCC_TME_TS_ARES] = { 0x100c0, 2 },
3019 [GCC_TME_SLOW_ARES] = { 0x100d0, 2 },
3020 [GCC_TME_RTC_TOGGLE_ARES] = { 0x100d8, 2 },
3021 [GCC_TIC_ARES] = { 0x12004, 2 },
3022 [GCC_PRNG_AHB_ARES] = { 0x13024, 2 },
3023 [GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 },
3024 [GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 },
3025 [GCC_NSS_TS_ARES] = { 0x17018, 2 },
3026 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 },
3027 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 },
3028 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 },
3029 [GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 },
3030 [GCC_NSSCFG_ARES] = { 0x1702c, 2 },
3031 [GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 },
3032 [GCC_NSSCC_ARES] = { 0x17034, 2 },
3033 [GCC_MDIO_AHB_ARES] = { 0x17040, 2 },
3034 [GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 },
3035 [GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 },
3036 [GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 },
3037 [GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 },
3038 [GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 },
3039 [GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 },
3040 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 },
3041 [GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 },
3042 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 },
3043 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 },
3044 [GCC_DDRSS_ATB_ARES] = { 0x19004, 2 },
3045 [GCC_DDRSS_AHB_ARES] = { 0x19008, 2 },
3046 [GCC_GEMNOC_AHB_ARES] = { 0x1900c, 2 },
3047 [GCC_GEMNOC_Q6_AXI_ARES] = { 0x19010, 2 },
3048 [GCC_GEMNOC_NSSNOC_ARES] = { 0x19014, 2 },
3049 [GCC_GEMNOC_SNOC_ARES] = { 0x19018, 2 },
3050 [GCC_GEMNOC_APSS_ARES] = { 0x1901c, 2 },
3051 [GCC_GEMNOC_QOSGEN_EXTREF_ARES] = { 0x19024, 2 },
3052 [GCC_GEMNOC_TS_ARES] = { 0x19028, 2 },
3053 [GCC_DDRSS_SMS_SLOW_ARES] = { 0x1902c, 2 },
3054 [GCC_GEMNOC_CNOC_ARES] = { 0x19038, 2 },
3055 [GCC_GEMNOC_XO_DBG_ARES] = { 0x19040, 2 },
3056 [GCC_GEMNOC_ANOC_ARES] = { 0x19048, 2 },
3057 [GCC_DDRSS_LLCC_ATB_ARES] = { 0x1904c, 2 },
3058 [GCC_LLCC_TPDM_CFG_ARES] = { 0x19050, 2 },
3059 [GCC_TME_BUS_ARES] = { 0x1a014, 2 },
3060 [GCC_SEC_CTRL_ACC_ARES] = { 0x1a018, 2 },
3061 [GCC_SEC_CTRL_ARES] = { 0x1a020, 2 },
3062 [GCC_SEC_CTRL_SENSE_ARES] = { 0x1a028, 2 },
3063 [GCC_SEC_CTRL_AHB_ARES] = { 0x1a038, 2 },
3064 [GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES] = { 0x1a03c, 2 },
3065 [GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 },
3066 [GCC_TME_ATB_ARES] = { 0x1e030, 2 },
3067 [GCC_TME_DBGAPB_ARES] = { 0x1e034, 2 },
3068 [GCC_TME_DEBUG_ARES] = { 0x1e038, 2 },
3069 [GCC_TME_AT_ARES] = { 0x1e03C, 2 },
3070 [GCC_TME_APB_ARES] = { 0x1e040, 2 },
3071 [GCC_TME_DMI_DBG_HS_ARES] = { 0x1e044, 2 },
3072 [GCC_APSS_AHB_ARES] = { 0x24014, 2 },
3073 [GCC_APSS_AXI_ARES] = { 0x24018, 2 },
3074 [GCC_CPUSS_TRIG_ARES] = { 0x2401c, 2 },
3075 [GCC_APSS_DBG_ARES] = { 0x2402c, 2 },
3076 [GCC_APSS_TS_ARES] = { 0x24030, 2 },
3077 [GCC_APSS_ATB_ARES] = { 0x24034, 2 },
3078 [GCC_Q6_AXIM_ARES] = { 0x2500c, 2 },
3079 [GCC_Q6_AXIS_ARES] = { 0x25010, 2 },
3080 [GCC_Q6_AHB_ARES] = { 0x25014, 2 },
3081 [GCC_Q6_AHB_S_ARES] = { 0x25018, 2 },
3082 [GCC_Q6SS_ATBM_ARES] = { 0x2501c, 2 },
3083 [GCC_Q6_TSCTR_1TO2_ARES] = { 0x25020, 2 },
3084 [GCC_Q6SS_PCLKDBG_ARES] = { 0x25024, 2 },
3085 [GCC_Q6SS_TRIG_ARES] = { 0x25028, 2 },
3086 [GCC_Q6SS_BOOT_CBCR_ARES] = { 0x2502c, 2 },
3087 [GCC_WCSS_DBG_IFC_APB_ARES] = { 0x25038, 2 },
3088 [GCC_WCSS_DBG_IFC_ATB_ARES] = { 0x2503c, 2 },
3089 [GCC_WCSS_DBG_IFC_NTS_ARES] = { 0x25040, 2 },
3090 [GCC_WCSS_DBG_IFC_DAPBUS_ARES] = { 0x25044, 2 },
3091 [GCC_WCSS_DBG_IFC_APB_BDG_ARES] = { 0x25048, 2 },
3092 [GCC_WCSS_DBG_IFC_NTS_BDG_ARES] = { 0x25050, 2 },
3093 [GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES] = { 0x25054, 2 },
3094 [GCC_WCSS_ECAHB_ARES] = { 0x25058, 2 },
3095 [GCC_WCSS_ACMT_ARES] = { 0x2505c, 2 },
3096 [GCC_WCSS_AHB_S_ARES] = { 0x25060, 2 },
3097 [GCC_WCSS_AXI_M_ARES] = { 0x25064, 2 },
3098 [GCC_PCNOC_WAPSS_ARES] = { 0x25080, 2 },
3099 [GCC_SNOC_WAPSS_ARES] = { 0x25090, 2 },
3100 [GCC_LPASS_SWAY_ARES] = { 0x27014, 2 },
3101 [GCC_LPASS_CORE_AXIM_ARES] = { 0x27018, 2 },
3102 [GCC_PCIE0_AHB_ARES] = { 0x28030, 2 },
3103 [GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 },
3104 [GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 },
3105 [GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2},
3106 [GCC_PCIE0_PIPE_ARES] = { 0x28068, 2},
3107 [GCC_PCIE0_AUX_ARES] = { 0x28070, 2 },
3108 [GCC_PCIE1_AHB_ARES] = { 0x29030, 2 },
3109 [GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 },
3110 [GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 },
3111 [GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 },
3112 [GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 },
3113 [GCC_PCIE1_AUX_ARES] = { 0x29074, 2 },
3114 [GCC_PCIE2_AHB_ARES] = { 0x2a030, 2 },
3115 [GCC_PCIE2_AXI_M_ARES] = { 0x2a038, 2 },
3116 [GCC_PCIE2_AXI_S_ARES] = { 0x2a040, 2 },
3117 [GCC_PCIE2_AXI_S_BRIDGE_ARES] = { 0x2a048, 2 },
3118 [GCC_PCIE2_PIPE_ARES] = { 0x2a068, 2 },
3119 [GCC_PCIE2_AUX_ARES] = { 0x2a078, 2 },
3120 [GCC_PCIE3_AHB_ARES] = { 0x2b030, 2 },
3121 [GCC_PCIE3_AXI_M_ARES] = { 0x2b038, 2 },
3122 [GCC_PCIE3_AXI_S_ARES] = { 0x2b040, 2 },
3123 [GCC_PCIE3_AXI_S_BRIDGE_ARES] = { 0x2b048, 2 },
3124 [GCC_PCIE3_PIPE_ARES] = { 0x2b068, 2 },
3125 [GCC_PCIE3_AUX_ARES] = { 0x2b07C, 2 },
3126 [GCC_USB0_MASTER_ARES] = { 0x2c044, 2 },
3127 [GCC_USB0_AUX_ARES] = { 0x2c04c, 2 },
3128 [GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 },
3129 [GCC_USB0_PIPE_ARES] = { 0x2c054, 2 },
3130 [GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 },
3131 [GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 },
3132 [GCC_QDSS_AT_ARES] = { 0x2d034, 2 },
3133 [GCC_QDSS_STM_ARES] = { 0x2d03C, 2 },
3134 [GCC_QDSS_TRACECLKIN_ARES] = { 0x2d040, 2 },
3135 [GCC_QDSS_TSCTR_DIV2_ARES] = { 0x2d044, 2 },
3136 [GCC_QDSS_TSCTR_DIV3_ARES] = { 0x2d048, 2 },
3137 [GCC_QDSS_TSCTR_DIV4_ARES] = { 0x2d04c, 2 },
3138 [GCC_QDSS_TSCTR_DIV8_ARES] = { 0x2d050, 2 },
3139 [GCC_QDSS_TSCTR_DIV16_ARES] = { 0x2d054, 2 },
3140 [GCC_QDSS_DAP_ARES] = { 0x2d058, 2 },
3141 [GCC_QDSS_APB2JTAG_ARES] = { 0x2d05c, 2 },
3142 [GCC_QDSS_ETR_USB_ARES] = { 0x2d060, 2 },
3143 [GCC_QDSS_DAP_AHB_ARES] = { 0x2d064, 2 },
3144 [GCC_QDSS_CFG_AHB_ARES] = { 0x2d068, 2 },
3145 [GCC_QDSS_EUD_AT_ARES] = { 0x2d06c, 2 },
3146 [GCC_QDSS_TS_ARES] = { 0x2d078, 2 },
3147 [GCC_QDSS_USB_ARES] = { 0x2d07c, 2 },
3148 [GCC_SYS_NOC_AXI_ARES] = { 0x2e01c, 2 },
3149 [GCC_SNOC_QOSGEN_EXTREF_ARES] = { 0x2e020, 2 },
3150 [GCC_CNOC_LPASS_CFG_ARES] = { 0x2e028, 2 },
3151 [GCC_SYS_NOC_AT_ARES] = { 0x2e038, 2 },
3152 [GCC_SNOC_PCNOC_AHB_ARES] = { 0x2e03c, 2 },
3153 [GCC_SNOC_TME_ARES] = { 0x2e05c, 2 },
3154 [GCC_SNOC_XO_DCD_ARES] = { 0x2e060, 2 },
3155 [GCC_SNOC_TS_ARES] = { 0x2e068, 2 },
3156 [GCC_ANOC0_AXI_ARES] = { 0x2e078, 2 },
3157 [GCC_ANOC_PCIE0_1LANE_M_ARES] = { 0x2e07c, 2 },
3158 [GCC_ANOC_PCIE2_2LANE_M_ARES] = { 0x2e080, 2 },
3159 [GCC_ANOC_PCIE1_1LANE_M_ARES] = { 0x2e084, 2 },
3160 [GCC_ANOC_PCIE3_2LANE_M_ARES] = { 0x2e090, 2 },
3161 [GCC_ANOC_PCNOC_AHB_ARES] = { 0x2e094, 2 },
3162 [GCC_ANOC_QOSGEN_EXTREF_ARES] = { 0x2e098, 2 },
3163 [GCC_ANOC_XO_DCD_ARES] = { 0x2e09C, 2 },
3164 [GCC_SNOC_XO_DBG_ARES] = { 0x2e0a0, 2 },
3165 [GCC_AGGRNOC_ATB_ARES] = { 0x2e0ac, 2 },
3166 [GCC_AGGRNOC_TS_ARES] = { 0x2e0b0, 2 },
3167 [GCC_USB0_EUD_AT_ARES] = { 0x30004, 2 },
3168 [GCC_PCNOC_TIC_ARES] = { 0x31014, 2 },
3169 [GCC_PCNOC_AHB_ARES] = { 0x31018, 2 },
3170 [GCC_PCNOC_XO_DBG_ARES] = { 0x3101c, 2 },
3171 [GCC_SNOC_LPASS_ARES] = { 0x31020, 2 },
3172 [GCC_PCNOC_AT_ARES] = { 0x31024, 2 },
3173 [GCC_PCNOC_XO_DCD_ARES] = { 0x31028, 2 },
3174 [GCC_PCNOC_TS_ARES] = { 0x3102c, 2 },
3175 [GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES] = { 0x31034, 2 },
3176 [GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES] = { 0x3103c, 2 },
3177 [GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES] = { 0x31044, 2 },
3178 [GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES] = { 0x3104c, 2 },
3179 [GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES] = { 0x31054, 2 },
3180 [GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES] = { 0x3105c, 2 },
3181 [GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES] = { 0x31064, 2 },
3182 [GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES] = { 0x3106c, 2 },
3183 [GCC_Q6_AXIM_RESET] = { 0x2506c, 0 },
3184 [GCC_Q6_AXIS_RESET] = { 0x2506c, 1 },
3185 [GCC_Q6_AHB_S_RESET] = { 0x2506c, 2 },
3186 [GCC_Q6_AHB_RESET] = { 0x2506c, 3 },
3187 [GCC_Q6SS_DBG_RESET] = { 0x2506c, 4 },
3188 [GCC_WCSS_ECAHB_RESET] = { 0x25070, 0 },
3189 [GCC_WCSS_DBG_BDG_RESET] = { 0x25070, 1 },
3190 [GCC_WCSS_DBG_RESET] = { 0x25070, 2 },
3191 [GCC_WCSS_AXI_M_RESET] = { 0x25070, 3 },
3192 [GCC_WCSS_AHB_S_RESET] = { 0x25070, 4 },
3193 [GCC_WCSS_ACMT_RESET] = { 0x25070, 5 },
3194 [GCC_WCSSAON_RESET] = { 0x25074, 0 },
3195 [GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 },
3196 [GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 },
3197 [GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 },
3198 [GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 },
3199 [GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 },
3200 [GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 },
3201 [GCC_PCIE0_AUX_RESET] = { 0x28058, 6 },
3202 [GCC_PCIE0_AHB_RESET] = { 0x28058, 7 },
3203 [GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 },
3204 [GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 },
3205 [GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 },
3206 [GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 },
3207 [GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 },
3208 [GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 },
3209 [GCC_PCIE1_AUX_RESET] = { 0x29058, 6 },
3210 [GCC_PCIE1_AHB_RESET] = { 0x29058, 7 },
3211 [GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 },
3212 [GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 },
3213 [GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 },
3214 [GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 },
3215 [GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 },
3216 [GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 },
3217 [GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 },
3218 [GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 },
3219 [GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 },
3220 [GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 },
3221 [GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 },
3222 [GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 },
3223 [GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 },
3224 [GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 },
3225 [GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 },
3226 [GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 },
3227 [GCC_NSS_PARTIAL_RESET] = { 0x17078, 0 },
3228 [GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 },
3229 [GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 },
3230 [GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 },
3231 [GCC_USB1_BCR] = { 0x3C000, 0 },
3232 [GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 },
3259 .max_register = 0x3f024,