Lines Matching +full:0 +full:x26004
62 .offset = 0x21000,
65 .enable_reg = 0x0b000,
66 .enable_mask = BIT(0),
77 .offset = 0x4a000,
80 .enable_reg = 0x0b000,
92 .offset = 0x24000,
95 .enable_reg = 0x0b000,
107 .offset = 0x25000,
110 .enable_reg = 0x0b000,
122 .offset = 0x21000,
136 .offset = 0x4a000,
150 .offset = 0x24000,
164 .offset = 0x25000,
199 { P_XO, 0 },
210 { P_XO, 0 },
221 { P_XO, 0 },
233 { P_XO, 0 },
245 { P_XO, 0 },
258 { P_XO, 0 },
271 { P_XO, 0 },
283 { P_XO, 0 },
296 { P_XO, 0 },
310 { P_XO, 0 },
324 { P_XO, 0 },
331 { P_XO, 0 },
346 { P_XO, 0 },
362 { P_XO, 0 },
378 { P_XO, 0 },
394 { P_XO, 0 },
407 { P_PCIE20_PHY0_PIPE, 0 },
417 { P_PCIE20_PHY1_PIPE, 0 },
427 { P_USB3PHY_0_PIPE, 0 },
432 F(24000000, P_XO, 1, 0, 0),
433 F(100000000, P_GPLL0, 8, 0, 0),
438 .cmd_rcgr = 0x1f008,
451 F(50000000, P_GPLL0, 16, 0, 0),
456 .cmd_rcgr = 0x0200c,
469 .cmd_rcgr = 0x03000,
482 .cmd_rcgr = 0x04000,
496 F(4800000, P_XO, 5, 0, 0),
499 F(24000000, P_XO, 1, 0, 0),
500 F(50000000, P_GPLL0, 16, 0, 0),
505 .cmd_rcgr = 0x02024,
519 .cmd_rcgr = 0x03014,
533 .cmd_rcgr = 0x04014,
550 F(24000000, P_XO, 1, 0, 0),
564 .cmd_rcgr = 0x02044,
578 .cmd_rcgr = 0x03034,
592 F(160000000, P_GPLL0, 5, 0, 0),
597 .cmd_rcgr = 0x16004,
610 F(2500000, P_GEPHY_TX, 5, 0, 0),
611 F(24000000, P_XO, 1, 0, 0),
612 F(25000000, P_GEPHY_TX, 5, 0, 0),
613 F(125000000, P_GEPHY_TX, 1, 0, 0),
618 .cmd_rcgr = 0x68020,
631 .reg = 0x68420,
632 .shift = 0,
648 .cmd_rcgr = 0x68028,
661 .reg = 0x68424,
662 .shift = 0,
678 F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
679 F(24000000, P_XO, 1, 0, 0),
680 F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
681 F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
682 F(125000000, P_UNIPHY_RX, 1, 0, 0),
683 F(312500000, P_UNIPHY_RX, 1, 0, 0),
688 .cmd_rcgr = 0x68030,
701 .reg = 0x68430,
702 .shift = 0,
718 F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
719 F(24000000, P_XO, 1, 0, 0),
720 F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
721 F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
722 F(125000000, P_UNIPHY_TX, 1, 0, 0),
723 F(312500000, P_UNIPHY_TX, 1, 0, 0),
728 .cmd_rcgr = 0x68038,
741 .reg = 0x68434,
742 .shift = 0,
758 F(240000000, P_GPLL4, 5, 0, 0),
763 .cmd_rcgr = 0x68080,
776 F(200000000, P_GPLL0, 4, 0, 0),
781 .cmd_rcgr = 0x08004,
795 .cmd_rcgr = 0x09004,
809 .cmd_rcgr = 0x0a004,
823 F(133333334, P_GPLL0, 6, 0, 0),
828 .cmd_rcgr = 0x2e028,
841 F(66666667, P_GPLL0, 12, 0, 0),
846 .cmd_rcgr = 0x2e040,
859 F(2000000, P_XO, 12, 0, 0),
864 .cmd_rcgr = 0x75020,
878 F(240000000, P_GPLL4, 5, 0, 0),
883 .cmd_rcgr = 0x75050,
896 .cmd_rcgr = 0x76020,
910 .cmd_rcgr = 0x76050,
923 .reg = 0x7501c,
939 .reg = 0x7601c,
954 F(100000000, P_GPLL0, 8, 0, 0),
959 .cmd_rcgr = 0x27000,
986 F(240000000, P_GPLL4, 5, 0, 0),
991 .cmd_rcgr = 0x2900c,
1004 F(200000000, P_GPLL0, 4, 0, 0),
1009 .cmd_rcgr = 0x2902c,
1022 F(266666667, P_GPLL0, 3, 0, 0),
1027 .cmd_rcgr = 0x29048,
1040 F(600000000, P_GPLL4, 2, 0, 0),
1045 .cmd_rcgr = 0x29064,
1099 F(24000000, P_XO, 1, 0, 0),
1100 F(100000000, P_GPLL0, 8, 0, 0),
1101 F(200000000, P_GPLL0, 4, 0, 0),
1102 F(320000000, P_GPLL0, 2.5, 0, 0),
1107 .cmd_rcgr = 0x57010,
1122 F(24000000, P_XO, 1, 0, 0),
1124 F(96000000, P_GPLL2, 12, 0, 0),
1126 F(192000000, P_GPLL2, 6, 0, 0),
1127 F(200000000, P_GPLL0, 4, 0, 0),
1132 .cmd_rcgr = 0x42004,
1146 F(266666667, P_GPLL0, 3, 0, 0),
1151 .cmd_rcgr = 0x26004,
1178 F(400000000, P_GPLL0, 2, 0, 0),
1183 .cmd_rcgr = 0x68088,
1197 F(850000000, P_UBI32_PLL, 1, 0, 0),
1198 F(1000000000, P_UBI32_PLL, 1, 0, 0),
1203 .cmd_rcgr = 0x68100,
1217 .cmd_rcgr = 0x3e05c,
1236 .cmd_rcgr = 0x3e090,
1250 .cmd_rcgr = 0x3e00c,
1269 .cmd_rcgr = 0x3e020,
1283 .reg = 0x3e048,
1299 F(400000000, P_GPLL0, 2, 0, 0),
1304 .cmd_rcgr = 0x59120,
1317 F(133333333, P_GPLL0, 6, 0, 0),
1322 .cmd_rcgr = 0x59020,
1335 .halt_reg = 0x30000,
1337 .enable_reg = 0x30000,
1349 .halt_reg = 0x30018,
1351 .enable_reg = 0x30018,
1364 .halt_reg = 0x30030,
1366 .enable_reg = 0x30030,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x1f020,
1383 .enable_reg = 0x1f020,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0x01008,
1401 .enable_reg = 0x0b004,
1416 .halt_reg = 0x02008,
1418 .enable_reg = 0x02008,
1419 .enable_mask = BIT(0),
1433 .halt_reg = 0x02004,
1435 .enable_reg = 0x02004,
1436 .enable_mask = BIT(0),
1450 .halt_reg = 0x03010,
1452 .enable_reg = 0x03010,
1453 .enable_mask = BIT(0),
1467 .halt_reg = 0x0300c,
1469 .enable_reg = 0x0300c,
1470 .enable_mask = BIT(0),
1484 .halt_reg = 0x04010,
1486 .enable_reg = 0x04010,
1487 .enable_mask = BIT(0),
1501 .halt_reg = 0x0400c,
1503 .enable_reg = 0x0400c,
1504 .enable_mask = BIT(0),
1518 .halt_reg = 0x0203c,
1520 .enable_reg = 0x0203c,
1521 .enable_mask = BIT(0),
1535 .halt_reg = 0x0302c,
1537 .enable_reg = 0x0302c,
1538 .enable_mask = BIT(0),
1552 .halt_reg = 0x1c004,
1554 .enable_reg = 0x1c004,
1555 .enable_mask = BIT(0),
1564 .halt_reg = 0x56308,
1566 .enable_reg = 0x56308,
1567 .enable_mask = BIT(0),
1581 .halt_reg = 0x5630c,
1583 .enable_reg = 0x5630c,
1584 .enable_mask = BIT(0),
1598 .halt_reg = 0x16024,
1601 .enable_reg = 0x0b004,
1602 .enable_mask = BIT(0),
1616 .halt_reg = 0x16020,
1619 .enable_reg = 0x0b004,
1634 .halt_reg = 0x1601c,
1637 .enable_reg = 0x0b004,
1652 .halt_reg = 0x77004,
1654 .enable_reg = 0x77004,
1655 .enable_mask = BIT(0),
1669 .halt_reg = 0x56010,
1672 .enable_reg = 0x56010,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0x56014,
1690 .enable_reg = 0x56014,
1691 .enable_mask = BIT(0),
1705 .halt_reg = 0x68304,
1707 .enable_reg = 0x68304,
1708 .enable_mask = BIT(0),
1722 .halt_reg = 0x68300,
1724 .enable_reg = 0x68300,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x68240,
1741 .enable_reg = 0x68240,
1742 .enable_mask = BIT(0),
1756 .halt_reg = 0x68190,
1760 .enable_reg = 0x68190,
1761 .enable_mask = BIT(0),
1775 .halt_reg = 0x68244,
1777 .enable_reg = 0x68244,
1778 .enable_mask = BIT(0),
1792 .halt_reg = 0x68324,
1794 .enable_reg = 0x68324,
1795 .enable_mask = BIT(0),
1809 .halt_reg = 0x68320,
1811 .enable_reg = 0x68320,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0x68248,
1828 .enable_reg = 0x68248,
1829 .enable_mask = BIT(0),
1843 .halt_reg = 0x68310,
1845 .enable_reg = 0x68310,
1846 .enable_mask = BIT(0),
1860 .halt_reg = 0x6824c,
1862 .enable_reg = 0x6824c,
1863 .enable_mask = BIT(0),
1877 .halt_reg = 0x08000,
1879 .enable_reg = 0x08000,
1880 .enable_mask = BIT(0),
1894 .halt_reg = 0x09000,
1896 .enable_reg = 0x09000,
1897 .enable_mask = BIT(0),
1911 .halt_reg = 0x0a000,
1913 .enable_reg = 0x0a000,
1914 .enable_mask = BIT(0),
1928 .halt_reg = 0x2e048,
1931 .enable_reg = 0x2e048,
1932 .enable_mask = BIT(0),
1946 .halt_reg = 0x2e04c,
1948 .enable_reg = 0x2e04c,
1949 .enable_mask = BIT(0),
1963 .halt_reg = 0x58004,
1965 .enable_reg = 0x58004,
1966 .enable_mask = BIT(0),
1980 .halt_reg = 0x58014,
1982 .enable_reg = 0x58014,
1983 .enable_mask = BIT(0),
1997 .halt_reg = 0x75010,
1999 .enable_reg = 0x75010,
2000 .enable_mask = BIT(0),
2014 .halt_reg = 0x75014,
2016 .enable_reg = 0x75014,
2017 .enable_mask = BIT(0),
2031 .halt_reg = 0x75008,
2033 .enable_reg = 0x75008,
2034 .enable_mask = BIT(0),
2048 .halt_reg = 0x75048,
2050 .enable_reg = 0x75048,
2051 .enable_mask = BIT(0),
2065 .halt_reg = 0x7500c,
2067 .enable_reg = 0x7500c,
2068 .enable_mask = BIT(0),
2082 .halt_reg = 0x75018,
2086 .enable_reg = 0x75018,
2087 .enable_mask = BIT(0),
2101 .halt_reg = 0x76010,
2103 .enable_reg = 0x76010,
2104 .enable_mask = BIT(0),
2118 .halt_reg = 0x76014,
2120 .enable_reg = 0x76014,
2121 .enable_mask = BIT(0),
2135 .halt_reg = 0x76008,
2137 .enable_reg = 0x76008,
2138 .enable_mask = BIT(0),
2152 .halt_reg = 0x76048,
2154 .enable_reg = 0x76048,
2155 .enable_mask = BIT(0),
2169 .halt_reg = 0x7600c,
2171 .enable_reg = 0x7600c,
2172 .enable_mask = BIT(0),
2186 .halt_reg = 0x76018,
2190 .enable_reg = 0x76018,
2191 .enable_mask = BIT(0),
2205 .halt_reg = 0x13004,
2208 .enable_reg = 0x0b004,
2223 .halt_reg = 0x59138,
2225 .enable_reg = 0x59138,
2226 .enable_mask = BIT(0),
2240 .halt_reg = 0x5914c,
2242 .enable_reg = 0x5914c,
2243 .enable_mask = BIT(0),
2257 .halt_reg = 0x5913c,
2259 .enable_reg = 0x5913c,
2260 .enable_mask = BIT(0),
2274 .halt_reg = 0x59150,
2276 .enable_reg = 0x59150,
2277 .enable_mask = BIT(0),
2291 .halt_reg = 0x59154,
2293 .enable_reg = 0x59154,
2294 .enable_mask = BIT(0),
2308 .halt_reg = 0x59148,
2310 .enable_reg = 0x59148,
2311 .enable_mask = BIT(0),
2325 .halt_reg = 0x59144,
2327 .enable_reg = 0x59144,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x59140,
2344 .enable_reg = 0x59140,
2345 .enable_mask = BIT(0),
2359 .halt_reg = 0x59128,
2361 .enable_reg = 0x59128,
2362 .enable_mask = BIT(0),
2376 .halt_reg = 0x29024,
2378 .enable_reg = 0x29024,
2379 .enable_mask = BIT(0),
2393 .halt_reg = 0x29084,
2395 .enable_reg = 0x29084,
2396 .enable_mask = BIT(0),
2410 .halt_reg = 0x29008,
2412 .enable_reg = 0x29008,
2413 .enable_mask = BIT(0),
2427 .halt_reg = 0x29004,
2429 .enable_reg = 0x29004,
2430 .enable_mask = BIT(0),
2444 .halt_reg = 0x29028,
2446 .enable_reg = 0x29028,
2447 .enable_mask = BIT(0),
2461 .halt_reg = 0x29020,
2463 .enable_reg = 0x29020,
2464 .enable_mask = BIT(0),
2478 .halt_reg = 0x29044,
2480 .enable_reg = 0x29044,
2481 .enable_mask = BIT(0),
2495 .halt_reg = 0x29060,
2497 .enable_reg = 0x29060,
2498 .enable_mask = BIT(0),
2512 .halt_reg = 0x2908c,
2514 .enable_reg = 0x2908c,
2515 .enable_mask = BIT(0),
2529 .halt_reg = 0x57024,
2531 .enable_reg = 0x57024,
2532 .enable_mask = BIT(0),
2546 .halt_reg = 0x57020,
2548 .enable_reg = 0x57020,
2549 .enable_mask = BIT(0),
2563 .halt_reg = 0x5701c,
2565 .enable_reg = 0x5701c,
2566 .enable_mask = BIT(0),
2580 .halt_reg = 0x4201c,
2582 .enable_reg = 0x4201c,
2583 .enable_mask = BIT(0),
2597 .halt_reg = 0x42018,
2599 .enable_reg = 0x42018,
2600 .enable_mask = BIT(0),
2614 .halt_reg = 0x260a0,
2616 .enable_reg = 0x260a0,
2617 .enable_mask = BIT(0),
2631 .halt_reg = 0x26084,
2633 .enable_reg = 0x26084,
2634 .enable_mask = BIT(0),
2648 .halt_reg = 0x260a4,
2650 .enable_reg = 0x260a4,
2651 .enable_mask = BIT(0),
2665 .halt_reg = 0x26088,
2667 .enable_reg = 0x26088,
2668 .enable_mask = BIT(0),
2682 .halt_reg = 0x26074,
2684 .enable_reg = 0x26074,
2685 .enable_mask = BIT(0),
2699 .halt_reg = 0x26078,
2701 .enable_reg = 0x26078,
2702 .enable_mask = BIT(0),
2716 .halt_reg = 0x26094,
2718 .enable_reg = 0x26094,
2719 .enable_mask = BIT(0),
2733 .halt_reg = 0x26048,
2735 .enable_reg = 0x26048,
2736 .enable_mask = BIT(0),
2750 .halt_reg = 0x2604c,
2752 .enable_reg = 0x2604c,
2753 .enable_mask = BIT(0),
2767 .halt_reg = 0x26024,
2769 .enable_reg = 0x26024,
2770 .enable_mask = BIT(0),
2784 .halt_reg = 0x26040,
2786 .enable_reg = 0x26040,
2787 .enable_mask = BIT(0),
2801 .halt_reg = 0x26034,
2803 .enable_reg = 0x26034,
2804 .enable_mask = BIT(0),
2818 .halt_reg = 0x68200,
2821 .enable_reg = 0x68200,
2822 .enable_mask = BIT(0),
2836 .halt_reg = 0x68160,
2839 .enable_reg = 0x68160,
2840 .enable_mask = BIT(0),
2854 .halt_reg = 0x68214,
2857 .enable_reg = 0x68214,
2858 .enable_mask = BIT(0),
2872 .halt_reg = 0x68210,
2875 .enable_reg = 0x68210,
2876 .enable_mask = BIT(0),
2890 .halt_reg = 0x68204,
2893 .enable_reg = 0x68204,
2894 .enable_mask = BIT(0),
2908 .halt_reg = 0x68208,
2911 .enable_reg = 0x68208,
2912 .enable_mask = BIT(0),
2926 .halt_reg = 0x56108,
2928 .enable_reg = 0x56108,
2929 .enable_mask = BIT(0),
2943 .halt_reg = 0x56110,
2945 .enable_reg = 0x56110,
2946 .enable_mask = BIT(0),
2960 .halt_reg = 0x56114,
2962 .enable_reg = 0x56114,
2963 .enable_mask = BIT(0),
2977 .halt_reg = 0x5610c,
2979 .enable_reg = 0x5610c,
2980 .enable_mask = BIT(0),
2994 .halt_reg = 0x3e044,
2996 .enable_reg = 0x3e044,
2997 .enable_mask = BIT(0),
3011 .halt_reg = 0x3e04c,
3014 .enable_reg = 0x3e04c,
3015 .enable_mask = BIT(0),
3029 .halt_reg = 0x3e050,
3031 .enable_reg = 0x3e050,
3032 .enable_mask = BIT(0),
3046 .halt_reg = 0x3e000,
3048 .enable_reg = 0x3e000,
3049 .enable_mask = BIT(0),
3063 .halt_reg = 0x3e008,
3065 .enable_reg = 0x3e008,
3066 .enable_mask = BIT(0),
3080 .halt_reg = 0x3e080,
3082 .enable_reg = 0x3e080,
3083 .enable_mask = BIT(0),
3097 .halt_reg = 0x3e004,
3099 .enable_reg = 0x3e004,
3100 .enable_mask = BIT(0),
3114 .halt_reg = 0x3e040,
3117 .enable_reg = 0x3e040,
3118 .enable_mask = BIT(0),
3132 .halt_reg = 0x59064,
3134 .enable_reg = 0x59064,
3135 .enable_mask = BIT(0),
3149 .halt_reg = 0x59034,
3151 .enable_reg = 0x59034,
3152 .enable_mask = BIT(0),
3166 .halt_reg = 0x5903c,
3168 .enable_reg = 0x5903c,
3169 .enable_mask = BIT(0),
3183 .halt_reg = 0x59068,
3185 .enable_reg = 0x59068,
3186 .enable_mask = BIT(0),
3200 .halt_reg = 0x59050,
3202 .enable_reg = 0x59050,
3203 .enable_mask = BIT(0),
3217 .halt_reg = 0x59040,
3219 .enable_reg = 0x59040,
3220 .enable_mask = BIT(0),
3234 .halt_reg = 0x59054,
3236 .enable_reg = 0x59054,
3237 .enable_mask = BIT(0),
3251 .halt_reg = 0x59044,
3253 .enable_reg = 0x59044,
3254 .enable_mask = BIT(0),
3268 .halt_reg = 0x59060,
3270 .enable_reg = 0x59060,
3271 .enable_mask = BIT(0),
3285 .halt_reg = 0x5905c,
3287 .enable_reg = 0x5905c,
3288 .enable_mask = BIT(0),
3302 .halt_reg = 0x59058,
3304 .enable_reg = 0x59058,
3305 .enable_mask = BIT(0),
3319 .halt_reg = 0x59048,
3321 .enable_reg = 0x59048,
3322 .enable_mask = BIT(0),
3336 .halt_reg = 0x59038,
3338 .enable_reg = 0x59038,
3339 .enable_mask = BIT(0),
3362 .l = 0x29,
3363 .alpha = 0xaaaaaaaa,
3364 .alpha_hi = 0xaa,
3365 .config_ctl_val = 0x4001075b,
3366 .main_output_mask = BIT(0),
3369 .vco_val = 0x1,
3371 .test_ctl_val = 0x0,
3372 .test_ctl_hi_val = 0x0,
3552 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3553 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3554 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3555 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3556 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3557 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3558 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3559 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3560 [GCC_BTSS_BCR] = { 0x1c000, 0 },
3561 [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3562 [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3563 [GCC_CE_BCR] = { 0x33014, 0 },
3564 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3565 [GCC_DCC_BCR] = { 0x77000, 0 },
3566 [GCC_DCD_BCR] = { 0x2a000, 0 },
3567 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
3568 [GCC_EDPD_BCR] = { 0x3a000, 0 },
3569 [GCC_GEPHY_BCR] = { 0x56000, 0 },
3570 [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3571 [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3572 [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3573 [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3574 [GCC_GMAC0_BCR] = { 0x19000, 0 },
3575 [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3576 [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3577 [GCC_GMAC1_BCR] = { 0x19100, 0 },
3578 [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3579 [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3580 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3581 [GCC_LPASS_BCR] = { 0x2e000, 0 },
3582 [GCC_MDIO0_BCR] = { 0x58000, 0 },
3583 [GCC_MDIO1_BCR] = { 0x58010, 0 },
3584 [GCC_MPM_BCR] = { 0x2c000, 0 },
3585 [GCC_PCIE0_BCR] = { 0x75004, 0 },
3586 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3587 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3588 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3589 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3590 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3591 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3592 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3593 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3594 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3595 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3596 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3597 [GCC_PCIE1_BCR] = { 0x76004, 0 },
3598 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3599 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3600 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3601 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3602 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3603 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3604 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3605 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3606 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3607 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3608 [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3609 [GCC_PCNOC_BCR] = { 0x27018, 0 },
3610 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3611 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3612 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3613 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3614 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3615 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3616 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3617 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3618 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3619 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3620 [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3621 [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3622 [GCC_PRNG_BCR] = { 0x13000, 0 },
3623 [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3624 [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3625 [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3626 [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3627 [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3628 [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3629 [GCC_QDSS_BCR] = { 0x29000, 0 },
3630 [GCC_QPIC_BCR] = { 0x57018, 0 },
3631 [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3632 [GCC_SDCC1_BCR] = { 0x42000, 0 },
3633 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3634 [GCC_SPDM_BCR] = { 0x2f000, 0 },
3635 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3636 [GCC_TCSR_BCR] = { 0x28000, 0 },
3637 [GCC_TLMM_BCR] = { 0x34000, 0 },
3638 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
3639 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3640 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3641 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3642 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3643 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3644 [GCC_UBI32_BCR] = { 0x19064, 0 },
3645 [GCC_UNIPHY_BCR] = { 0x56100, 0 },
3646 [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3647 [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3648 [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3649 [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3650 [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3651 [GCC_USB0_BCR] = { 0x3e070, 0 },
3652 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3653 [GCC_WCSS_BCR] = { 0x18000, 0 },
3654 [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3655 [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3656 [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3657 [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3658 [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3659 [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3660 [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3661 [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3662 [GCC_WCSSAON_RESET] = { 0x59010, 0},
3663 [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3676 .max_register = 0x7fffc,