1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
18 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
21 #include "clk-regmap.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
25 #include "clk-regmap-divider.h"
45  * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
61  * struct clk_fepll - clk divider corresponds to FEPLL clocks
90 	const struct clk_fepll_vco *pll_vco = pll_div->pll_vco;  in clk_fepll_vco_calc_rate()
94 	regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv);  in clk_fepll_vco_calc_rate()
95 	refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) &  in clk_fepll_vco_calc_rate()
96 		    (BIT(pll_vco->refclkdiv_width) - 1);  in clk_fepll_vco_calc_rate()
97 	fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) &  in clk_fepll_vco_calc_rate()
98 		  (BIT(pll_vco->fdbkdiv_width) - 1);  in clk_fepll_vco_calc_rate()
135 	f = qcom_find_freq(pll->freq_tbl, rate);  in clk_cpu_div_round_rate()
137 		return -EINVAL;  in clk_cpu_div_round_rate()
139 	p_hw = clk_hw_get_parent_by_index(hw, f->src);  in clk_cpu_div_round_rate()
142 	return f->freq;  in clk_cpu_div_round_rate()
157 	f = qcom_find_freq(pll->freq_tbl, rate);  in clk_cpu_div_set_rate()
159 		return -EINVAL;  in clk_cpu_div_set_rate()
161 	mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;  in clk_cpu_div_set_rate()
162 	regmap_update_bits(pll->cdiv.clkr.regmap,  in clk_cpu_div_set_rate()
163 			   pll->cdiv.reg, mask,  in clk_cpu_div_set_rate()
164 			   f->pre_div << pll->cdiv.shift);  in clk_cpu_div_set_rate()
188 	regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_cpu_div_recalc_rate()
189 	cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_cpu_div_recalc_rate()
266 	if (pll->fixed_div) {  in clk_regmap_clk_div_recalc_rate()
267 		pre_div = pll->fixed_div;  in clk_regmap_clk_div_recalc_rate()
269 		regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_regmap_clk_div_recalc_rate()
270 		cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_regmap_clk_div_recalc_rate()
272 		for (clkt = pll->div_table; clkt->div; clkt++) {  in clk_regmap_clk_div_recalc_rate()
273 			if (clkt->val == cdiv)  in clk_regmap_clk_div_recalc_rate()
274 				pre_div = clkt->div;  in clk_regmap_clk_div_recalc_rate()
1713 	{ .compatible = "qcom,gcc-ipq4019" },
1743 	return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk,  in gcc_ipq4019_probe()
1750 		.name	= "qcom,gcc-ipq4019",
1767 MODULE_ALIAS("platform:gcc-ipq4019");
1769 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");