Lines Matching +full:0 +full:x2e000
112 .reg = 0x2e020,
120 .reg = 0x2f020,
144 return 0;
173 return 0;
216 { 384000000, P_XO, 0xd, 0, 0 },
217 { 413000000, P_XO, 0xc, 0, 0 },
218 { 448000000, P_XO, 0xb, 0, 0 },
219 { 488000000, P_XO, 0xa, 0, 0 },
220 { 512000000, P_XO, 0x9, 0, 0 },
221 { 537000000, P_XO, 0x8, 0, 0 },
222 { 565000000, P_XO, 0x7, 0, 0 },
223 { 597000000, P_XO, 0x6, 0, 0 },
224 { 632000000, P_XO, 0x5, 0, 0 },
225 { 672000000, P_XO, 0x4, 0, 0 },
226 { 716000000, P_XO, 0x3, 0, 0 },
227 { 768000000, P_XO, 0x2, 0, 0 },
228 { 823000000, P_XO, 0x1, 0, 0 },
229 { 896000000, P_XO, 0x0, 0, 0 },
234 .cdiv.reg = 0x2e020,
238 .enable_reg = 0x2e000,
239 .enable_mask = BIT(0),
371 { 0, 15 },
379 .cdiv.reg = 0x2f020,
398 .cdiv.reg = 0x2f020,
417 { P_XO, 0 },
429 F(48000000, P_XO, 1, 0, 0),
430 F(100000000, P_FEPLL200, 2, 0, 0),
435 .cmd_rcgr = 0x21024,
448 .halt_reg = 0x21030,
450 .enable_reg = 0x21030,
451 .enable_mask = BIT(0),
465 { P_XO, 0 },
475 F(48000000, P_XO, 1, 0, 0),
476 F(200000000, P_FEPLL200, 1, 0, 0),
481 .cmd_rcgr = 0x1b000,
495 .halt_reg = 0x1b010,
497 .enable_reg = 0x1b010,
498 .enable_mask = BIT(0),
511 .halt_reg = 0x1b00C,
513 .enable_reg = 0x1b00C,
514 .enable_mask = BIT(0),
532 .cmd_rcgr = 0x200c,
545 .halt_reg = 0x2008,
547 .enable_reg = 0x2008,
548 .enable_mask = BIT(0),
561 .cmd_rcgr = 0x3000,
574 .halt_reg = 0x3010,
576 .enable_reg = 0x3010,
577 .enable_mask = BIT(0),
590 { P_XO, 0 },
606 F(48000000, P_XO, 1, 0, 0),
611 .cmd_rcgr = 0x2024,
625 .halt_reg = 0x2004,
627 .enable_reg = 0x2004,
628 .enable_mask = BIT(0),
641 .cmd_rcgr = 0x3014,
655 .halt_reg = 0x300c,
657 .enable_reg = 0x300c,
658 .enable_mask = BIT(0),
680 F(48000000, P_XO, 1, 0, 0),
685 .cmd_rcgr = 0x2044,
699 .halt_reg = 0x203c,
701 .enable_reg = 0x203c,
702 .enable_mask = BIT(0),
715 .cmd_rcgr = 0x3034,
729 .halt_reg = 0x302c,
731 .enable_reg = 0x302c,
732 .enable_mask = BIT(0),
745 F(1250000, P_FEPLL200, 1, 16, 0),
746 F(2500000, P_FEPLL200, 1, 8, 0),
747 F(5000000, P_FEPLL200, 1, 4, 0),
752 .cmd_rcgr = 0x8004,
766 .halt_reg = 0x8000,
768 .enable_reg = 0x8000,
769 .enable_mask = BIT(0),
782 .cmd_rcgr = 0x9004,
796 .halt_reg = 0x9000,
798 .enable_reg = 0x9000,
799 .enable_mask = BIT(0),
812 .cmd_rcgr = 0xa004,
826 .halt_reg = 0xa000,
828 .enable_reg = 0xa000,
829 .enable_mask = BIT(0),
842 { P_XO, 0 },
855 F(400000, P_XO, 1, 1, 0),
860 F(192000000, P_DDRPLL, 1, 0, 0),
865 .cmd_rcgr = 0x18004,
879 F(48000000, P_XO, 1, 0, 0),
880 F(200000000, P_FEPLL200, 1, 0, 0),
881 F(384000000, P_DDRPLLAPSS, 1, 0, 0),
882 F(413000000, P_DDRPLLAPSS, 1, 0, 0),
883 F(448000000, P_DDRPLLAPSS, 1, 0, 0),
884 F(488000000, P_DDRPLLAPSS, 1, 0, 0),
885 F(500000000, P_FEPLL500, 1, 0, 0),
886 F(512000000, P_DDRPLLAPSS, 1, 0, 0),
887 F(537000000, P_DDRPLLAPSS, 1, 0, 0),
888 F(565000000, P_DDRPLLAPSS, 1, 0, 0),
889 F(597000000, P_DDRPLLAPSS, 1, 0, 0),
890 F(632000000, P_DDRPLLAPSS, 1, 0, 0),
891 F(672000000, P_DDRPLLAPSS, 1, 0, 0),
892 F(716000000, P_DDRPLLAPSS, 1, 0, 0),
897 { P_XO, 0 },
911 .cmd_rcgr = 0x1900c,
925 F(48000000, P_XO, 1, 0, 0),
926 F(100000000, P_FEPLL200, 2, 0, 0),
931 .cmd_rcgr = 0x19014,
944 .halt_reg = 0x19004,
947 .enable_reg = 0x6000,
961 .halt_reg = 0x1008,
964 .enable_reg = 0x6000,
977 .halt_reg = 0x2103c,
979 .enable_reg = 0x2103c,
980 .enable_mask = BIT(0),
994 .halt_reg = 0x1300c,
996 .enable_reg = 0x1300c,
997 .enable_mask = BIT(0),
1010 .halt_reg = 0x16024,
1013 .enable_reg = 0x6000,
1014 .enable_mask = BIT(0),
1026 .halt_reg = 0x16020,
1029 .enable_reg = 0x6000,
1042 .halt_reg = 0x1601c,
1045 .enable_reg = 0x6000,
1058 { P_XO, 0 },
1068 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1073 .cmd_rcgr = 0x12000,
1086 .halt_reg = 0x12010,
1088 .enable_reg = 0x12010,
1089 .enable_mask = BIT(0),
1102 .halt_reg = 0xe004,
1105 .enable_reg = 0x6000,
1118 .halt_reg = 0xe008,
1120 .enable_reg = 0xe008,
1121 .enable_mask = BIT(0),
1133 .halt_reg = 0x1d00c,
1135 .enable_reg = 0x1d00c,
1136 .enable_mask = BIT(0),
1148 .halt_reg = 0x1d004,
1150 .enable_reg = 0x1d004,
1151 .enable_mask = BIT(0),
1163 .halt_reg = 0x1d008,
1165 .enable_reg = 0x1d008,
1166 .enable_mask = BIT(0),
1178 .halt_reg = 0x13004,
1181 .enable_reg = 0x6000,
1194 .halt_reg = 0x1c008,
1196 .enable_reg = 0x1c008,
1197 .enable_mask = BIT(0),
1209 .halt_reg = 0x1c004,
1211 .enable_reg = 0x1c004,
1212 .enable_mask = BIT(0),
1224 .halt_reg = 0x18010,
1226 .enable_reg = 0x18010,
1227 .enable_mask = BIT(0),
1239 .halt_reg = 0x1800c,
1241 .enable_reg = 0x1800c,
1242 .enable_mask = BIT(0),
1255 .halt_reg = 0x5004,
1258 .enable_reg = 0x6000,
1271 .halt_reg = 0x1e00c,
1273 .enable_reg = 0x1e00c,
1274 .enable_mask = BIT(0),
1286 .halt_reg = 0x1e010,
1288 .enable_reg = 0x1e010,
1289 .enable_mask = BIT(0),
1303 F(2000000, P_FEPLL200, 10, 0, 0),
1308 .cmd_rcgr = 0x1e000,
1321 .halt_reg = 0x1e014,
1323 .enable_reg = 0x1e014,
1324 .enable_mask = BIT(0),
1337 .halt_reg = 0x1e028,
1339 .enable_reg = 0x1e028,
1340 .enable_mask = BIT(0),
1352 .halt_reg = 0x1e02C,
1354 .enable_reg = 0x1e02C,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x1e030,
1371 .enable_reg = 0x1e030,
1372 .enable_mask = BIT(0),
1385 { P_XO, 0 },
1395 F(48000000, P_XO, 1, 0, 0),
1396 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1401 .cmd_rcgr = 0x1f000,
1415 .halt_reg = 0x1f00C,
1417 .enable_reg = 0x1f00C,
1418 .enable_mask = BIT(0),
1431 .halt_reg = 0x1f00C,
1433 .enable_reg = 0x1f00C,
1434 .enable_mask = BIT(0),
1449 .halt_reg = 0x1f010,
1451 .enable_reg = 0x1f010,
1452 .enable_mask = BIT(0),
1466 { P_XO, 0 },
1476 F(48000000, P_XO, 1, 0, 0),
1477 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1482 .cmd_rcgr = 0x20000,
1495 .halt_reg = 0x2000c,
1497 .enable_reg = 0x2000c,
1498 .enable_mask = BIT(0),
1511 .halt_reg = 0x2000c,
1513 .enable_reg = 0x2000c,
1514 .enable_mask = BIT(0),
1529 .halt_reg = 0x20010,
1531 .enable_reg = 0x20010,
1532 .enable_mask = BIT(0),
1619 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
1620 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
1621 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
1622 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
1623 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1624 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
1625 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
1626 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
1627 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
1628 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
1629 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1630 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
1631 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
1632 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
1633 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
1634 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
1635 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
1636 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
1637 [PCIE_AHB_ARES] = { 0x1d010, 10 },
1638 [PCIE_PWR_ARES] = { 0x1d010, 9 },
1639 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
1640 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
1641 [PCIE_PHY_ARES] = { 0x1d010, 6 },
1642 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
1643 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
1644 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
1645 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
1646 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1647 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
1648 [ESS_RESET] = { 0x12008, 0},
1649 [GCC_BLSP1_BCR] = {0x01000, 0},
1650 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
1651 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
1652 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
1653 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
1654 [GCC_BIMC_BCR] = {0x04000, 0},
1655 [GCC_TLMM_BCR] = {0x05000, 0},
1656 [GCC_IMEM_BCR] = {0x0E000, 0},
1657 [GCC_ESS_BCR] = {0x12008, 0},
1658 [GCC_PRNG_BCR] = {0x13000, 0},
1659 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
1660 [GCC_CRYPTO_BCR] = {0x16000, 0},
1661 [GCC_SDCC1_BCR] = {0x18000, 0},
1662 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
1663 [GCC_AUDIO_BCR] = {0x1B008, 0},
1664 [GCC_QPIC_BCR] = {0x1C000, 0},
1665 [GCC_PCIE_BCR] = {0x1D000, 0},
1666 [GCC_USB2_BCR] = {0x1E008, 0},
1667 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
1668 [GCC_USB3_BCR] = {0x1E024, 0},
1669 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
1670 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
1671 [GCC_PCNOC_BCR] = {0x2102C, 0},
1672 [GCC_DCD_BCR] = {0x21038, 0},
1673 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
1674 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
1675 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
1676 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
1677 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
1678 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
1679 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
1680 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
1681 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
1682 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
1683 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
1684 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
1685 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
1686 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
1687 [GCC_TCSR_BCR] = {0x22000, 0},
1688 [GCC_MPM_BCR] = {0x24000, 0},
1689 [GCC_SPDM_BCR] = {0x25000, 0},
1690 [ESS_MAC1_ARES] = {0x1200C, 0},
1691 [ESS_MAC2_ARES] = {0x1200C, 1},
1692 [ESS_MAC3_ARES] = {0x1200C, 2},
1693 [ESS_MAC4_ARES] = {0x1200C, 3},
1694 [ESS_MAC5_ARES] = {0x1200C, 4},
1695 [ESS_PSGMII_ARES] = {0x1200C, 5},
1702 .max_register = 0x2ffff,
1724 int err = 0;