Lines Matching +full:0 +full:x94000
133 .offset = 0x0,
136 .enable_reg = 0x62040,
137 .enable_mask = BIT(0),
150 { 0x1, 2 },
155 .offset = 0x0,
172 .offset = 0x1000,
175 .enable_reg = 0x62040,
189 .offset = 0xe000,
192 .enable_reg = 0x62040,
206 { 0x1, 2 },
211 .offset = 0xe000,
228 .offset = 0x4000,
231 .enable_reg = 0x62040,
245 .offset = 0x5000,
248 .enable_reg = 0x62040,
262 .offset = 0x7000,
265 .enable_reg = 0x62040,
279 .offset = 0x8000,
282 .enable_reg = 0x62040,
296 .offset = 0x9000,
299 .enable_reg = 0x62040,
319 { P_BI_TCXO, 0 },
331 { P_BI_TCXO, 0 },
345 { P_BI_TCXO, 0 },
355 { P_BI_TCXO, 0 },
371 { P_BI_TCXO, 0 },
385 { P_BI_TCXO, 0 },
393 { P_BI_TCXO, 0 },
407 { P_BI_TCXO, 0 },
419 { P_BI_TCXO, 0 },
429 { P_BI_TCXO, 0 },
443 { P_BI_TCXO, 0 },
455 { P_BI_TCXO, 0 },
471 { P_BI_TCXO, 0 },
487 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
497 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
507 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
517 { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
529 { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
543 { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
555 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
565 { P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
575 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
585 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
595 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
605 { P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 },
615 { P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
625 { P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
635 { P_BI_TCXO, 0 },
649 { P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
659 { P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
669 { P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
679 { P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
689 { P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 0 },
699 { P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 0 },
709 { P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
719 { P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
729 { P_BI_TCXO, 0 },
743 { P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
753 { P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
763 { P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
773 { P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
783 { P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
793 { P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
803 { P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
813 { P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
823 { P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
833 { P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
843 .reg = 0xdc088,
857 .reg = 0x941b4,
871 .reg = 0x881a4,
885 .reg = 0xc309c,
899 .reg = 0x8a1a4,
913 .reg = 0x7706c,
914 .shift = 0,
928 .reg = 0x770f0,
929 .shift = 0,
943 .reg = 0x7705c,
944 .shift = 0,
958 .reg = 0x2b0b8,
959 .shift = 0,
973 .reg = 0x2d0c4,
974 .shift = 0,
988 .reg = 0xe00bc,
989 .shift = 0,
1003 .reg = 0x9a07c,
1004 .shift = 0,
1018 .reg = 0x9a084,
1019 .shift = 0,
1033 .reg = 0x3f08c,
1034 .shift = 0,
1048 .reg = 0xe207c,
1049 .shift = 0,
1063 .reg = 0xe107c,
1064 .shift = 0,
1078 .reg = 0x2b080,
1079 .shift = 0,
1093 .reg = 0x2b134,
1094 .shift = 0,
1108 .reg = 0x2b0f0,
1109 .shift = 0,
1123 .reg = 0x2b120,
1124 .shift = 0,
1138 .reg = 0x2b0c0,
1139 .shift = 0,
1153 .reg = 0x2b0d4,
1154 .shift = 0,
1168 .reg = 0x2b100,
1169 .shift = 0,
1183 .reg = 0x2d08c,
1184 .shift = 0,
1198 .reg = 0x2d154,
1199 .shift = 0,
1213 .reg = 0x2d114,
1214 .shift = 0,
1228 .reg = 0x2d140,
1229 .shift = 0,
1243 .reg = 0x2d0e4,
1244 .shift = 0,
1258 .reg = 0x2d0f8,
1259 .shift = 0,
1273 .reg = 0x2d124,
1274 .shift = 0,
1288 .reg = 0xe0084,
1289 .shift = 0,
1303 .reg = 0xe013c,
1304 .shift = 0,
1318 .reg = 0xe00f4,
1319 .shift = 0,
1333 .reg = 0xe0124,
1334 .shift = 0,
1348 .reg = 0xe00c4,
1349 .shift = 0,
1363 .reg = 0xe00d8,
1364 .shift = 0,
1378 .reg = 0xe0104,
1379 .shift = 0,
1393 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1394 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1395 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1400 .cmd_rcgr = 0x64004,
1415 .cmd_rcgr = 0x92004,
1430 .cmd_rcgr = 0x93004,
1445 F(19200000, P_BI_TCXO, 1, 0, 0),
1450 .cmd_rcgr = 0xc8168,
1465 F(19200000, P_BI_TCXO, 1, 0, 0),
1466 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1471 .cmd_rcgr = 0xc803c,
1472 .mnd_width = 0,
1486 .cmd_rcgr = 0x2e168,
1501 .cmd_rcgr = 0x2e03c,
1502 .mnd_width = 0,
1516 .cmd_rcgr = 0xc0168,
1531 .cmd_rcgr = 0xc003c,
1532 .mnd_width = 0,
1546 .cmd_rcgr = 0xdc08c,
1561 .cmd_rcgr = 0xdc070,
1562 .mnd_width = 0,
1576 .cmd_rcgr = 0x941b8,
1591 .cmd_rcgr = 0x94088,
1592 .mnd_width = 0,
1606 .cmd_rcgr = 0x881a8,
1621 .cmd_rcgr = 0x88078,
1622 .mnd_width = 0,
1636 .cmd_rcgr = 0xc30a0,
1651 .cmd_rcgr = 0xc3084,
1652 .mnd_width = 0,
1666 .cmd_rcgr = 0x8a1a8,
1681 .cmd_rcgr = 0x8a078,
1682 .mnd_width = 0,
1696 .cmd_rcgr = 0x6c01c,
1711 .cmd_rcgr = 0x7501c,
1726 .cmd_rcgr = 0xd3018,
1741 .cmd_rcgr = 0xd2018,
1756 .cmd_rcgr = 0xd4018,
1771 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1776 .cmd_rcgr = 0x33010,
1777 .mnd_width = 0,
1793 F(19200000, P_BI_TCXO, 1, 0, 0),
1798 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1801 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1802 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1803 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1804 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1805 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1818 .cmd_rcgr = 0xe7044,
1829 F(19200000, P_BI_TCXO, 1, 0, 0),
1834 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1837 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1838 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1839 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1840 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1853 .cmd_rcgr = 0xe7170,
1870 .cmd_rcgr = 0x287a0,
1887 .cmd_rcgr = 0x288d0,
1904 .cmd_rcgr = 0x2866c,
1915 F(19200000, P_BI_TCXO, 1, 0, 0),
1920 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1923 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1924 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1937 .cmd_rcgr = 0x28014,
1954 .cmd_rcgr = 0x28150,
1965 F(19200000, P_BI_TCXO, 1, 0, 0),
1970 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1973 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1986 .cmd_rcgr = 0x282b4,
2003 .cmd_rcgr = 0x283f0,
2020 .cmd_rcgr = 0x28540,
2037 .cmd_rcgr = 0xb37a0,
2054 .cmd_rcgr = 0xb38d0,
2071 .cmd_rcgr = 0xb366c,
2088 .cmd_rcgr = 0xb3014,
2105 .cmd_rcgr = 0xb3150,
2122 .cmd_rcgr = 0xb32b4,
2139 .cmd_rcgr = 0xb33f0,
2156 .cmd_rcgr = 0xb3540,
2173 .cmd_rcgr = 0xb47a0,
2190 .cmd_rcgr = 0xb48d0,
2207 .cmd_rcgr = 0xb466c,
2224 .cmd_rcgr = 0xb4014,
2241 .cmd_rcgr = 0xb4150,
2258 .cmd_rcgr = 0xb42b4,
2275 .cmd_rcgr = 0xb43f0,
2292 .cmd_rcgr = 0xb4540,
2302 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2303 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
2304 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2305 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
2310 .cmd_rcgr = 0xb001c,
2326 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2327 F(75000000, P_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
2332 .cmd_rcgr = 0xdf01c,
2347 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2348 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2349 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2350 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2355 .cmd_rcgr = 0x77038,
2370 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2371 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2372 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2377 .cmd_rcgr = 0x77090,
2378 .mnd_width = 0,
2392 .cmd_rcgr = 0x770c4,
2393 .mnd_width = 0,
2407 .cmd_rcgr = 0x770a8,
2408 .mnd_width = 0,
2422 F(60000000, P_GCC_GPLL14_OUT_MAIN, 10, 0, 0),
2423 F(120000000, P_GCC_GPLL14_OUT_MAIN, 5, 0, 0),
2428 .cmd_rcgr = 0xbc030,
2443 .cmd_rcgr = 0xbc048,
2444 .mnd_width = 0,
2458 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
2459 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
2460 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
2461 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
2466 .cmd_rcgr = 0x9a03c,
2481 .cmd_rcgr = 0x9a054,
2482 .mnd_width = 0,
2496 .cmd_rcgr = 0x3f04c,
2511 .cmd_rcgr = 0x3f064,
2512 .mnd_width = 0,
2526 .cmd_rcgr = 0xe203c,
2541 .cmd_rcgr = 0xe2054,
2542 .mnd_width = 0,
2556 .cmd_rcgr = 0xe103c,
2571 .cmd_rcgr = 0xe1054,
2572 .mnd_width = 0,
2586 .cmd_rcgr = 0x9a088,
2587 .mnd_width = 0,
2601 .cmd_rcgr = 0x3f090,
2602 .mnd_width = 0,
2616 .cmd_rcgr = 0xe2080,
2617 .mnd_width = 0,
2631 .cmd_rcgr = 0xe1080,
2632 .mnd_width = 0,
2646 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
2647 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2648 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2653 .cmd_rcgr = 0x2b02c,
2668 F(19200000, P_BI_TCXO, 1, 0, 0),
2669 F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
2670 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
2675 .cmd_rcgr = 0x2b104,
2676 .mnd_width = 0,
2690 .cmd_rcgr = 0x2b0a0,
2691 .mnd_width = 0,
2705 .cmd_rcgr = 0x2b084,
2706 .mnd_width = 0,
2720 .cmd_rcgr = 0x2d02c,
2735 F(19200000, P_BI_TCXO, 1, 0, 0),
2736 F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2737 F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2742 .cmd_rcgr = 0x2d128,
2743 .mnd_width = 0,
2757 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2758 F(311000000, P_GCC_GPLL5_OUT_MAIN, 3, 0, 0),
2763 .cmd_rcgr = 0x2d0c8,
2764 .mnd_width = 0,
2778 .cmd_rcgr = 0x2d0ac,
2779 .mnd_width = 0,
2793 .cmd_rcgr = 0x2d090,
2794 .mnd_width = 0,
2808 .cmd_rcgr = 0xe002c,
2823 .cmd_rcgr = 0xe0108,
2824 .mnd_width = 0,
2838 .cmd_rcgr = 0xe00a4,
2839 .mnd_width = 0,
2853 .cmd_rcgr = 0xe0088,
2854 .mnd_width = 0,
2868 .reg = 0x94070,
2869 .shift = 0,
2883 .reg = 0x88060,
2884 .shift = 0,
2898 .reg = 0xc306c,
2899 .shift = 0,
2913 .reg = 0x8a060,
2914 .shift = 0,
2928 .reg = 0xe7024,
2929 .shift = 0,
2943 .reg = 0xe7038,
2944 .shift = 0,
2958 .reg = 0x2828c,
2959 .shift = 0,
2973 .reg = 0x282a0,
2974 .shift = 0,
2988 .reg = 0x2852c,
2989 .shift = 0,
3003 .reg = 0xb328c,
3004 .shift = 0,
3018 .reg = 0xb32a0,
3019 .shift = 0,
3033 .reg = 0xb352c,
3034 .shift = 0,
3048 .reg = 0xb428c,
3049 .shift = 0,
3063 .reg = 0xb42a0,
3064 .shift = 0,
3078 .reg = 0xb452c,
3079 .shift = 0,
3093 .reg = 0xbc174,
3094 .shift = 0,
3108 .reg = 0x9a06c,
3109 .shift = 0,
3123 .reg = 0x3f07c,
3124 .shift = 0,
3138 .reg = 0xe206c,
3139 .shift = 0,
3153 .reg = 0xe106c,
3154 .shift = 0,
3168 .halt_reg = 0xdc0bc,
3171 .enable_reg = 0x62008,
3181 .halt_reg = 0x941ec,
3184 .enable_reg = 0x62008,
3194 .halt_reg = 0x881d0,
3197 .enable_reg = 0x62008,
3207 .halt_reg = 0xc30d0,
3210 .enable_reg = 0x62008,
3220 .halt_reg = 0x8a1d0,
3223 .enable_reg = 0x62008,
3233 .halt_reg = 0x77000,
3235 .hwcg_reg = 0x77000,
3238 .enable_reg = 0x77000,
3239 .enable_mask = BIT(0),
3253 .halt_reg = 0xbc17c,
3255 .hwcg_reg = 0xbc17c,
3258 .enable_reg = 0xbc17c,
3259 .enable_mask = BIT(0),
3273 .halt_reg = 0x9a004,
3275 .hwcg_reg = 0x9a004,
3278 .enable_reg = 0x9a004,
3279 .enable_mask = BIT(0),
3293 .halt_reg = 0x3f00c,
3295 .hwcg_reg = 0x3f00c,
3298 .enable_reg = 0x3f00c,
3299 .enable_mask = BIT(0),
3313 .halt_reg = 0xe2004,
3315 .hwcg_reg = 0xe2004,
3318 .enable_reg = 0xe2004,
3319 .enable_mask = BIT(0),
3333 .halt_reg = 0xe1004,
3335 .hwcg_reg = 0xe1004,
3338 .enable_reg = 0xe1004,
3339 .enable_mask = BIT(0),
3353 .halt_reg = 0x2b000,
3355 .hwcg_reg = 0x2b000,
3358 .enable_reg = 0x2b000,
3359 .enable_mask = BIT(0),
3373 .halt_reg = 0x2d000,
3375 .hwcg_reg = 0x2d000,
3378 .enable_reg = 0x2d000,
3379 .enable_mask = BIT(0),
3393 .halt_reg = 0xe0000,
3395 .hwcg_reg = 0xe0000,
3398 .enable_reg = 0xe0000,
3399 .enable_mask = BIT(0),
3413 .halt_reg = 0x9b02c,
3415 .hwcg_reg = 0x9b02c,
3418 .enable_reg = 0x9b02c,
3419 .enable_mask = BIT(0),
3428 .halt_reg = 0x9b030,
3430 .hwcg_reg = 0x9b030,
3433 .enable_reg = 0x9b030,
3434 .enable_mask = BIT(0),
3443 .halt_reg = 0x9b044,
3446 .enable_reg = 0x9b044,
3447 .enable_mask = BIT(0),
3456 .halt_reg = 0x34038,
3458 .hwcg_reg = 0x34038,
3461 .enable_reg = 0x62020,
3471 .halt_reg = 0x26014,
3473 .hwcg_reg = 0x26014,
3476 .enable_reg = 0x26014,
3477 .enable_mask = BIT(0),
3486 .halt_reg = 0x26028,
3488 .hwcg_reg = 0x26028,
3491 .enable_reg = 0x26028,
3492 .enable_mask = BIT(0),
3501 .halt_reg = 0x82004,
3503 .hwcg_reg = 0x82004,
3506 .enable_reg = 0x62008,
3516 .halt_reg = 0xba2ec,
3518 .hwcg_reg = 0xba2ec,
3521 .enable_reg = 0x62008,
3531 .halt_reg = 0xbc178,
3533 .hwcg_reg = 0xbc178,
3536 .enable_reg = 0xbc178,
3537 .enable_mask = BIT(0),
3551 .halt_reg = 0x9a000,
3553 .hwcg_reg = 0x9a000,
3556 .enable_reg = 0x9a000,
3557 .enable_mask = BIT(0),
3571 .halt_reg = 0x3f000,
3573 .hwcg_reg = 0x3f000,
3576 .enable_reg = 0x3f000,
3577 .enable_mask = BIT(0),
3591 .halt_reg = 0xe2000,
3593 .hwcg_reg = 0xe2000,
3596 .enable_reg = 0xe2000,
3597 .enable_mask = BIT(0),
3611 .halt_reg = 0xe1000,
3613 .hwcg_reg = 0xe1000,
3616 .enable_reg = 0xe1000,
3617 .enable_mask = BIT(0),
3631 .halt_reg = 0x3f004,
3633 .hwcg_reg = 0x3f004,
3636 .enable_reg = 0x62008,
3646 .halt_reg = 0x3f008,
3648 .hwcg_reg = 0x3f008,
3651 .enable_reg = 0x62008,
3661 .halt_reg = 0x27008,
3664 .enable_reg = 0x27008,
3665 .enable_mask = BIT(0),
3675 .halt_reg = 0x9b004,
3677 .hwcg_reg = 0x9b004,
3680 .enable_reg = 0x9b004,
3681 .enable_mask = BIT(0),
3690 .halt_reg = 0x9b008,
3692 .hwcg_reg = 0x9b008,
3695 .enable_reg = 0x9b008,
3696 .enable_mask = BIT(0),
3705 .halt_reg = 0x9b01c,
3707 .hwcg_reg = 0x9b01c,
3710 .enable_reg = 0x9b01c,
3711 .enable_mask = BIT(0),
3720 .halt_reg = 0x9b024,
3723 .enable_reg = 0x9b024,
3724 .enable_mask = BIT(0),
3733 .halt_reg = 0x64000,
3736 .enable_reg = 0x64000,
3737 .enable_mask = BIT(0),
3751 .halt_reg = 0x92000,
3754 .enable_reg = 0x92000,
3755 .enable_mask = BIT(0),
3769 .halt_reg = 0x93000,
3772 .enable_reg = 0x93000,
3773 .enable_mask = BIT(0),
3787 .halt_reg = 0x71010,
3789 .hwcg_reg = 0x71010,
3792 .enable_reg = 0x71010,
3793 .enable_mask = BIT(0),
3802 .halt_reg = 0x71024,
3804 .hwcg_reg = 0x71024,
3807 .enable_reg = 0x62038,
3808 .enable_mask = BIT(0),
3822 .halt_reg = 0x7102c,
3824 .hwcg_reg = 0x7102c,
3827 .enable_reg = 0x62038,
3842 .halt_reg = 0xc8018,
3845 .enable_reg = 0x62010,
3860 .halt_reg = 0xba4a8,
3862 .hwcg_reg = 0xba4a8,
3865 .enable_reg = 0x62010,
3875 .halt_reg = 0xba498,
3877 .hwcg_reg = 0xba498,
3880 .enable_reg = 0x62010,
3890 .halt_reg = 0xc8038,
3893 .enable_reg = 0x62010,
3908 .halt_reg = 0xc8028,
3911 .enable_reg = 0x62010,
3926 .halt_reg = 0xba488,
3928 .hwcg_reg = 0xba488,
3931 .enable_reg = 0x62010,
3941 .halt_reg = 0xba484,
3944 .enable_reg = 0x62010,
3954 .halt_reg = 0x2e018,
3957 .enable_reg = 0x62010,
3972 .halt_reg = 0xba480,
3974 .hwcg_reg = 0xba480,
3977 .enable_reg = 0x62010,
3987 .halt_reg = 0xba470,
3989 .hwcg_reg = 0xba470,
3992 .enable_reg = 0x62010,
4002 .halt_reg = 0x2e038,
4005 .enable_reg = 0x62010,
4020 .halt_reg = 0x2e028,
4023 .enable_reg = 0x62010,
4038 .halt_reg = 0xba460,
4040 .hwcg_reg = 0xba460,
4043 .enable_reg = 0x62010,
4053 .halt_reg = 0xba45c,
4056 .enable_reg = 0x62010,
4066 .halt_reg = 0xc0018,
4069 .enable_reg = 0x62018,
4070 .enable_mask = BIT(0),
4084 .halt_reg = 0xba4d0,
4086 .hwcg_reg = 0xba4d0,
4089 .enable_reg = 0x62010,
4099 .halt_reg = 0xba4c0,
4101 .hwcg_reg = 0xba4c0,
4104 .enable_reg = 0x62010,
4114 .halt_reg = 0xc0038,
4117 .enable_reg = 0x62018,
4132 .halt_reg = 0xc0028,
4135 .enable_reg = 0x62018,
4150 .halt_reg = 0xba4b0,
4152 .hwcg_reg = 0xba4b0,
4155 .enable_reg = 0x62010,
4165 .halt_reg = 0xba4ac,
4168 .enable_reg = 0x62010,
4178 .halt_reg = 0xdc04c,
4180 .hwcg_reg = 0xdc04c,
4183 .enable_reg = 0x62028,
4198 .halt_reg = 0xba4f0,
4200 .hwcg_reg = 0xba4f0,
4203 .enable_reg = 0x62028,
4213 .halt_reg = 0xdc038,
4215 .hwcg_reg = 0xdc038,
4218 .enable_reg = 0x62028,
4228 .halt_reg = 0xdc06c,
4230 .hwcg_reg = 0xdc06c,
4233 .enable_reg = 0x62028,
4248 .halt_reg = 0xdc05c,
4250 .hwcg_reg = 0xdc05c,
4253 .enable_reg = 0x62028,
4268 .halt_reg = 0xdc024,
4270 .hwcg_reg = 0xdc024,
4273 .enable_reg = 0x62028,
4283 .halt_reg = 0xdc01c,
4285 .hwcg_reg = 0xdc01c,
4288 .enable_reg = 0x62028,
4298 .halt_reg = 0x94050,
4301 .enable_reg = 0x62028,
4316 .halt_reg = 0xba4f4,
4318 .hwcg_reg = 0xba4f4,
4321 .enable_reg = 0x62028,
4331 .halt_reg = 0x94038,
4333 .hwcg_reg = 0x94038,
4336 .enable_reg = 0x62028,
4346 .halt_reg = 0x94084,
4349 .enable_reg = 0x62028,
4364 .halt_reg = 0x94060,
4367 .enable_reg = 0x62028,
4382 .halt_reg = 0x94074,
4385 .enable_reg = 0x62028,
4400 .halt_reg = 0x94024,
4402 .hwcg_reg = 0x94024,
4405 .enable_reg = 0x62028,
4415 .halt_reg = 0x9401c,
4418 .enable_reg = 0x62028,
4428 .halt_reg = 0x88040,
4431 .enable_reg = 0x62030,
4446 .halt_reg = 0xba4fc,
4448 .hwcg_reg = 0xba4fc,
4451 .enable_reg = 0x62030,
4461 .halt_reg = 0x88030,
4463 .hwcg_reg = 0x88030,
4466 .enable_reg = 0x62030,
4476 .halt_reg = 0x88074,
4479 .enable_reg = 0x62030,
4494 .halt_reg = 0x88050,
4497 .enable_reg = 0x62030,
4512 .halt_reg = 0x88064,
4515 .enable_reg = 0x62030,
4530 .halt_reg = 0x88020,
4532 .hwcg_reg = 0x88020,
4535 .enable_reg = 0x62030,
4545 .halt_reg = 0x8801c,
4548 .enable_reg = 0x62030,
4558 .halt_reg = 0xc304c,
4561 .enable_reg = 0x62030,
4576 .halt_reg = 0xba4f8,
4578 .hwcg_reg = 0xba4f8,
4581 .enable_reg = 0x62030,
4591 .halt_reg = 0xc3038,
4593 .hwcg_reg = 0xc3038,
4596 .enable_reg = 0x62030,
4606 .halt_reg = 0xc3080,
4609 .enable_reg = 0x62030,
4624 .halt_reg = 0xc305c,
4627 .enable_reg = 0x62030,
4642 .halt_reg = 0xc3070,
4645 .enable_reg = 0x62030,
4660 .halt_reg = 0xc3024,
4662 .hwcg_reg = 0xc3024,
4665 .enable_reg = 0x62030,
4675 .halt_reg = 0xc301c,
4678 .enable_reg = 0x62030,
4688 .halt_reg = 0x8a040,
4691 .enable_reg = 0x62030,
4706 .halt_reg = 0xba500,
4708 .hwcg_reg = 0xba500,
4711 .enable_reg = 0x62030,
4721 .halt_reg = 0x8a030,
4723 .hwcg_reg = 0x8a030,
4726 .enable_reg = 0x62030,
4736 .halt_reg = 0x8a074,
4739 .enable_reg = 0x62030,
4754 .halt_reg = 0x8a050,
4757 .enable_reg = 0x62030,
4772 .halt_reg = 0x8a064,
4775 .enable_reg = 0x62030,
4790 .halt_reg = 0x8a020,
4792 .hwcg_reg = 0x8a020,
4795 .enable_reg = 0x62030,
4805 .halt_reg = 0x8a01c,
4808 .enable_reg = 0x62030,
4818 .halt_reg = 0xba2ac,
4821 .enable_reg = 0x62008,
4831 .halt_reg = 0xba2a8,
4834 .enable_reg = 0x62008,
4844 .halt_reg = 0xba2b0,
4846 .hwcg_reg = 0xba2b0,
4849 .enable_reg = 0x62008,
4859 .halt_reg = 0xba2b8,
4861 .hwcg_reg = 0xba2b8,
4864 .enable_reg = 0x62008,
4874 .halt_reg = 0xba2c0,
4876 .hwcg_reg = 0xba2c0,
4879 .enable_reg = 0x62008,
4889 .halt_reg = 0xba2a4,
4891 .hwcg_reg = 0xba2a4,
4894 .enable_reg = 0x62008,
4904 .halt_reg = 0x6c038,
4906 .hwcg_reg = 0x6c038,
4909 .enable_reg = 0x62028,
4924 .halt_reg = 0x75034,
4927 .enable_reg = 0x62028,
4942 .halt_reg = 0xd3030,
4945 .enable_reg = 0x62030,
4960 .halt_reg = 0xd2030,
4963 .enable_reg = 0x62030,
4978 .halt_reg = 0xd4030,
4981 .enable_reg = 0x62030,
4996 .halt_reg = 0xb8004,
4998 .hwcg_reg = 0xb8004,
5001 .enable_reg = 0x62038,
5011 .halt_reg = 0xb8008,
5014 .enable_reg = 0x62038,
5024 .halt_reg = 0x3300c,
5027 .enable_reg = 0x3300c,
5028 .enable_mask = BIT(0),
5042 .halt_reg = 0x33004,
5044 .hwcg_reg = 0x33004,
5047 .enable_reg = 0x33004,
5048 .enable_mask = BIT(0),
5057 .halt_reg = 0x33008,
5060 .enable_reg = 0x33008,
5061 .enable_mask = BIT(0),
5070 .halt_reg = 0x9b048,
5072 .hwcg_reg = 0x9b048,
5075 .enable_reg = 0x9b048,
5076 .enable_mask = BIT(0),
5085 .halt_reg = 0x26010,
5087 .hwcg_reg = 0x26010,
5090 .enable_reg = 0x26010,
5091 .enable_mask = BIT(0),
5100 .halt_reg = 0x26008,
5102 .hwcg_reg = 0x26008,
5105 .enable_reg = 0x26008,
5106 .enable_mask = BIT(0),
5115 .halt_reg = 0x2600c,
5117 .hwcg_reg = 0x2600c,
5120 .enable_reg = 0x2600c,
5121 .enable_mask = BIT(0),
5130 .halt_reg = 0x71008,
5132 .hwcg_reg = 0x71008,
5135 .enable_reg = 0x71008,
5136 .enable_mask = BIT(0),
5145 .halt_reg = 0xdc018,
5147 .hwcg_reg = 0xdc018,
5150 .enable_reg = 0x62028,
5160 .halt_reg = 0x94018,
5162 .hwcg_reg = 0x94018,
5165 .enable_reg = 0x62028,
5175 .halt_reg = 0x88018,
5177 .hwcg_reg = 0x88018,
5180 .enable_reg = 0x62030,
5190 .halt_reg = 0xc3018,
5192 .hwcg_reg = 0xc3018,
5195 .enable_reg = 0x62030,
5196 .enable_mask = BIT(0),
5205 .halt_reg = 0x8a018,
5207 .hwcg_reg = 0x8a018,
5210 .enable_reg = 0x62030,
5220 .halt_reg = 0x32018,
5222 .hwcg_reg = 0x32018,
5225 .enable_reg = 0x32018,
5226 .enable_mask = BIT(0),
5235 .halt_reg = 0x32008,
5237 .hwcg_reg = 0x32008,
5240 .enable_reg = 0x32008,
5241 .enable_mask = BIT(0),
5250 .halt_reg = 0x32014,
5252 .hwcg_reg = 0x32014,
5255 .enable_reg = 0x32014,
5256 .enable_mask = BIT(0),
5265 .halt_reg = 0x32010,
5267 .hwcg_reg = 0x32010,
5270 .enable_reg = 0x32010,
5271 .enable_mask = BIT(0),
5280 .halt_reg = 0x3200c,
5282 .hwcg_reg = 0x3200c,
5285 .enable_reg = 0x3200c,
5286 .enable_mask = BIT(0),
5295 .halt_reg = 0xc5040,
5298 .enable_reg = 0x62018,
5308 .halt_reg = 0xc502c,
5311 .enable_reg = 0x62018,
5321 .halt_reg = 0xe7004,
5323 .hwcg_reg = 0xe7004,
5326 .enable_reg = 0xe7004,
5327 .enable_mask = BIT(0),
5336 .halt_reg = 0xe7040,
5339 .enable_reg = 0x62018,
5354 .halt_reg = 0xe729c,
5357 .enable_reg = 0x62018,
5372 .halt_reg = 0xe7014,
5375 .enable_reg = 0x62018,
5390 .halt_reg = 0xe7028,
5393 .enable_reg = 0x62018,
5408 .halt_reg = 0xc5028,
5410 .hwcg_reg = 0xc5028,
5413 .enable_reg = 0x62018,
5423 .halt_reg = 0xe703c,
5426 .enable_reg = 0x62018,
5436 .halt_reg = 0xc5448,
5439 .enable_reg = 0x62020,
5449 .halt_reg = 0xc5434,
5452 .enable_reg = 0x62020,
5462 .halt_reg = 0x2879c,
5465 .enable_reg = 0x62020,
5480 .halt_reg = 0x288cc,
5483 .enable_reg = 0x62020,
5498 .halt_reg = 0x28798,
5501 .enable_reg = 0x62020,
5516 .halt_reg = 0x28004,
5519 .enable_reg = 0x62020,
5534 .halt_reg = 0x28140,
5537 .enable_reg = 0x62020,
5552 .halt_reg = 0x2827c,
5555 .enable_reg = 0x62020,
5570 .halt_reg = 0x28290,
5573 .enable_reg = 0x62020,
5588 .halt_reg = 0x282a4,
5591 .enable_reg = 0x62020,
5606 .halt_reg = 0x283e0,
5609 .enable_reg = 0x62020,
5624 .halt_reg = 0x2851c,
5627 .enable_reg = 0x62020,
5642 .halt_reg = 0x28530,
5645 .enable_reg = 0x62020,
5660 .halt_reg = 0xc5198,
5663 .enable_reg = 0x62018,
5673 .halt_reg = 0xc5184,
5676 .enable_reg = 0x62018,
5686 .halt_reg = 0xb379c,
5689 .enable_reg = 0x62018,
5704 .halt_reg = 0xb38cc,
5707 .enable_reg = 0x62018,
5722 .halt_reg = 0xb3798,
5725 .enable_reg = 0x62018,
5740 .halt_reg = 0xb3004,
5743 .enable_reg = 0x62018,
5758 .halt_reg = 0xb3140,
5761 .enable_reg = 0x62018,
5776 .halt_reg = 0xb327c,
5779 .enable_reg = 0x62018,
5794 .halt_reg = 0xb3290,
5797 .enable_reg = 0x62018,
5812 .halt_reg = 0xb32a4,
5815 .enable_reg = 0x62018,
5830 .halt_reg = 0xb33e0,
5833 .enable_reg = 0x62018,
5848 .halt_reg = 0xb351c,
5851 .enable_reg = 0x62018,
5866 .halt_reg = 0xb3530,
5869 .enable_reg = 0x62018,
5884 .halt_reg = 0xc52f0,
5887 .enable_reg = 0x62018,
5897 .halt_reg = 0xc52dc,
5900 .enable_reg = 0x62018,
5910 .halt_reg = 0xb479c,
5913 .enable_reg = 0x62020,
5928 .halt_reg = 0xb48cc,
5931 .enable_reg = 0x62020,
5946 .halt_reg = 0xb4798,
5949 .enable_reg = 0x62020,
5964 .halt_reg = 0xb4004,
5967 .enable_reg = 0x62018,
5982 .halt_reg = 0xb4140,
5985 .enable_reg = 0x62018,
6000 .halt_reg = 0xb427c,
6003 .enable_reg = 0x62020,
6004 .enable_mask = BIT(0),
6018 .halt_reg = 0xb4290,
6021 .enable_reg = 0x62020,
6036 .halt_reg = 0xb42a4,
6039 .enable_reg = 0x62020,
6054 .halt_reg = 0xb43e0,
6057 .enable_reg = 0x62020,
6072 .halt_reg = 0xb451c,
6075 .enable_reg = 0x62020,
6090 .halt_reg = 0xb4530,
6093 .enable_reg = 0x62020,
6108 .halt_reg = 0xc542c,
6110 .hwcg_reg = 0xc542c,
6113 .enable_reg = 0x62020,
6123 .halt_reg = 0xc5430,
6125 .hwcg_reg = 0xc5430,
6128 .enable_reg = 0x62020,
6138 .halt_reg = 0xc517c,
6140 .hwcg_reg = 0xc517c,
6143 .enable_reg = 0x62018,
6153 .halt_reg = 0xc5180,
6155 .hwcg_reg = 0xc5180,
6158 .enable_reg = 0x62018,
6168 .halt_reg = 0xc52d4,
6170 .hwcg_reg = 0xc52d4,
6173 .enable_reg = 0x62018,
6183 .halt_reg = 0xc52d8,
6185 .hwcg_reg = 0xc52d8,
6188 .enable_reg = 0x62018,
6198 .halt_reg = 0xb0014,
6201 .enable_reg = 0xb0014,
6202 .enable_mask = BIT(0),
6211 .halt_reg = 0xb0004,
6214 .enable_reg = 0xb0004,
6215 .enable_mask = BIT(0),
6229 .halt_reg = 0xdf014,
6232 .enable_reg = 0xdf014,
6233 .enable_mask = BIT(0),
6242 .halt_reg = 0xdf004,
6245 .enable_reg = 0xdf004,
6246 .enable_mask = BIT(0),
6260 .halt_reg = 0xba504,
6262 .hwcg_reg = 0xba504,
6265 .enable_reg = 0xba504,
6266 .enable_mask = BIT(0),
6275 .halt_reg = 0x7701c,
6277 .hwcg_reg = 0x7701c,
6280 .enable_reg = 0x7701c,
6281 .enable_mask = BIT(0),
6295 .halt_reg = 0x77080,
6297 .hwcg_reg = 0x77080,
6300 .enable_reg = 0x77080,
6301 .enable_mask = BIT(0),
6315 .halt_reg = 0x770c0,
6317 .hwcg_reg = 0x770c0,
6320 .enable_reg = 0x770c0,
6321 .enable_mask = BIT(0),
6335 .halt_reg = 0x77034,
6338 .enable_reg = 0x77034,
6339 .enable_mask = BIT(0),
6353 .halt_reg = 0x770dc,
6356 .enable_reg = 0x770dc,
6357 .enable_mask = BIT(0),
6371 .halt_reg = 0x77030,
6374 .enable_reg = 0x77030,
6375 .enable_mask = BIT(0),
6389 .halt_reg = 0x77070,
6391 .hwcg_reg = 0x77070,
6394 .enable_reg = 0x77070,
6395 .enable_mask = BIT(0),
6409 .halt_reg = 0xbc018,
6412 .enable_reg = 0xbc018,
6413 .enable_mask = BIT(0),
6427 .halt_reg = 0xbc02c,
6430 .enable_reg = 0xbc02c,
6431 .enable_mask = BIT(0),
6445 .halt_reg = 0xbc028,
6448 .enable_reg = 0xbc028,
6449 .enable_mask = BIT(0),
6458 .halt_reg = 0x9a024,
6461 .enable_reg = 0x9a024,
6462 .enable_mask = BIT(0),
6476 .halt_reg = 0x9a038,
6479 .enable_reg = 0x9a038,
6480 .enable_mask = BIT(0),
6494 .halt_reg = 0x9a034,
6497 .enable_reg = 0x9a034,
6498 .enable_mask = BIT(0),
6507 .halt_reg = 0x3f030,
6510 .enable_reg = 0x3f030,
6511 .enable_mask = BIT(0),
6525 .halt_reg = 0x3f048,
6528 .enable_reg = 0x3f048,
6529 .enable_mask = BIT(0),
6543 .halt_reg = 0x3f044,
6546 .enable_reg = 0x3f044,
6547 .enable_mask = BIT(0),
6556 .halt_reg = 0xe2024,
6559 .enable_reg = 0xe2024,
6560 .enable_mask = BIT(0),
6574 .halt_reg = 0xe2038,
6577 .enable_reg = 0xe2038,
6578 .enable_mask = BIT(0),
6592 .halt_reg = 0xe2034,
6595 .enable_reg = 0xe2034,
6596 .enable_mask = BIT(0),
6605 .halt_reg = 0xe1024,
6608 .enable_reg = 0xe1024,
6609 .enable_mask = BIT(0),
6623 .halt_reg = 0xe1038,
6626 .enable_reg = 0xe1038,
6627 .enable_mask = BIT(0),
6641 .halt_reg = 0xe1034,
6644 .enable_reg = 0xe1034,
6645 .enable_mask = BIT(0),
6654 .halt_reg = 0x9a070,
6657 .enable_reg = 0x9a070,
6658 .enable_mask = BIT(0),
6672 .halt_reg = 0x9a074,
6675 .enable_reg = 0x9a074,
6676 .enable_mask = BIT(0),
6690 .halt_reg = 0x9a078,
6693 .enable_reg = 0x9a078,
6694 .enable_mask = BIT(0),
6708 .halt_reg = 0x9a080,
6711 .enable_reg = 0x9a080,
6712 .enable_mask = BIT(0),
6726 .halt_reg = 0x3f080,
6729 .enable_reg = 0x3f080,
6730 .enable_mask = BIT(0),
6744 .halt_reg = 0x3f084,
6747 .enable_reg = 0x3f084,
6748 .enable_mask = BIT(0),
6762 .halt_reg = 0x3f088,
6764 .hwcg_reg = 0x3f088,
6767 .enable_reg = 0x3f088,
6768 .enable_mask = BIT(0),
6782 .halt_reg = 0xe2070,
6785 .enable_reg = 0xe2070,
6786 .enable_mask = BIT(0),
6800 .halt_reg = 0xe2074,
6803 .enable_reg = 0xe2074,
6804 .enable_mask = BIT(0),
6818 .halt_reg = 0xe2078,
6820 .hwcg_reg = 0xe2078,
6823 .enable_reg = 0xe2078,
6824 .enable_mask = BIT(0),
6838 .halt_reg = 0xe1070,
6841 .enable_reg = 0xe1070,
6842 .enable_mask = BIT(0),
6856 .halt_reg = 0xe1074,
6859 .enable_reg = 0xe1074,
6860 .enable_mask = BIT(0),
6874 .halt_reg = 0xe1078,
6876 .hwcg_reg = 0xe1078,
6879 .enable_reg = 0xe1078,
6880 .enable_mask = BIT(0),
6894 .halt_reg = 0xba450,
6896 .hwcg_reg = 0xba450,
6899 .enable_reg = 0xba450,
6900 .enable_mask = BIT(0),
6909 .halt_reg = 0x2b070,
6912 .enable_reg = 0x2b070,
6913 .enable_mask = BIT(0),
6927 .halt_reg = 0x2b124,
6930 .enable_reg = 0x2b124,
6931 .enable_mask = BIT(0),
6945 .halt_reg = 0x2b01c,
6948 .enable_reg = 0x2b01c,
6949 .enable_mask = BIT(0),
6963 .halt_reg = 0x2b0f4,
6966 .enable_reg = 0x2b0f4,
6967 .enable_mask = BIT(0),
6981 .halt_reg = 0x2b04c,
6984 .enable_reg = 0x62010,
6999 .halt_reg = 0x2b0c4,
7002 .enable_reg = 0x2b0c4,
7003 .enable_mask = BIT(0),
7017 .halt_reg = 0x2b0d8,
7020 .enable_reg = 0x2b0d8,
7021 .enable_mask = BIT(0),
7035 .halt_reg = 0x2b0bc,
7037 .hwcg_reg = 0x2b0bc,
7040 .enable_reg = 0x2b0bc,
7041 .enable_mask = BIT(0),
7055 .halt_reg = 0x2b048,
7058 .enable_reg = 0x2b048,
7059 .enable_mask = BIT(0),
7073 .halt_reg = 0x2b05c,
7076 .enable_reg = 0x2b05c,
7077 .enable_mask = BIT(0),
7091 .halt_reg = 0x2b09c,
7093 .hwcg_reg = 0x2b09c,
7096 .enable_reg = 0x2b09c,
7097 .enable_mask = BIT(0),
7111 .halt_reg = 0x2b06c,
7114 .enable_reg = 0x2b06c,
7115 .enable_mask = BIT(0),
7129 .halt_reg = 0xba454,
7131 .hwcg_reg = 0xba454,
7134 .enable_reg = 0xba454,
7135 .enable_mask = BIT(0),
7144 .halt_reg = 0x2d07c,
7147 .enable_reg = 0x2d07c,
7148 .enable_mask = BIT(0),
7162 .halt_reg = 0x2d144,
7165 .enable_reg = 0x2d144,
7166 .enable_mask = BIT(0),
7180 .halt_reg = 0x2d01c,
7183 .enable_reg = 0x2d01c,
7184 .enable_mask = BIT(0),
7198 .halt_reg = 0x2d118,
7201 .enable_reg = 0x2d118,
7202 .enable_mask = BIT(0),
7216 .halt_reg = 0x2d04c,
7219 .enable_reg = 0x62010,
7234 .halt_reg = 0x2d0e8,
7237 .enable_reg = 0x2d0e8,
7238 .enable_mask = BIT(0),
7252 .halt_reg = 0x2d0fc,
7255 .enable_reg = 0x2d0fc,
7256 .enable_mask = BIT(0),
7270 .halt_reg = 0x2d0e0,
7272 .hwcg_reg = 0x2d0e0,
7275 .enable_reg = 0x2d0e0,
7276 .enable_mask = BIT(0),
7290 .halt_reg = 0x2d048,
7293 .enable_reg = 0x2d048,
7294 .enable_mask = BIT(0),
7308 .halt_reg = 0x2d05c,
7311 .enable_reg = 0x2d05c,
7312 .enable_mask = BIT(0),
7326 .halt_reg = 0x2d0a8,
7328 .hwcg_reg = 0x2d0a8,
7331 .enable_reg = 0x2d0a8,
7332 .enable_mask = BIT(0),
7346 .halt_reg = 0x2d06c,
7349 .enable_reg = 0x2d06c,
7350 .enable_mask = BIT(0),
7364 .halt_reg = 0xba458,
7366 .hwcg_reg = 0xba458,
7369 .enable_reg = 0xba458,
7370 .enable_mask = BIT(0),
7379 .halt_reg = 0xe0070,
7382 .enable_reg = 0xe0070,
7383 .enable_mask = BIT(0),
7397 .halt_reg = 0xe0128,
7400 .enable_reg = 0xe0128,
7401 .enable_mask = BIT(0),
7415 .halt_reg = 0xe001c,
7418 .enable_reg = 0xe001c,
7419 .enable_mask = BIT(0),
7433 .halt_reg = 0xe00f8,
7436 .enable_reg = 0xe00f8,
7437 .enable_mask = BIT(0),
7451 .halt_reg = 0xe004c,
7454 .enable_reg = 0x62010,
7469 .halt_reg = 0xe00c8,
7472 .enable_reg = 0xe00c8,
7473 .enable_mask = BIT(0),
7487 .halt_reg = 0xe00dc,
7490 .enable_reg = 0xe00dc,
7491 .enable_mask = BIT(0),
7505 .halt_reg = 0xe00c0,
7507 .hwcg_reg = 0xe00c0,
7510 .enable_reg = 0xe00c0,
7511 .enable_mask = BIT(0),
7525 .halt_reg = 0xe0048,
7528 .enable_reg = 0xe0048,
7529 .enable_mask = BIT(0),
7543 .halt_reg = 0xe005c,
7546 .enable_reg = 0xe005c,
7547 .enable_mask = BIT(0),
7561 .halt_reg = 0xe00a0,
7563 .hwcg_reg = 0xe00a0,
7566 .enable_reg = 0xe00a0,
7567 .enable_mask = BIT(0),
7581 .halt_reg = 0xe006c,
7584 .enable_reg = 0xe006c,
7585 .enable_mask = BIT(0),
7599 .halt_reg = 0x3201c,
7601 .hwcg_reg = 0x3201c,
7604 .enable_reg = 0x3201c,
7605 .enable_mask = BIT(0),
7614 .halt_reg = 0x32030,
7616 .hwcg_reg = 0x32030,
7619 .enable_reg = 0x32030,
7620 .enable_mask = BIT(0),
7629 .halt_reg = 0x32044,
7631 .hwcg_reg = 0x32044,
7634 .enable_reg = 0x32044,
7635 .enable_mask = BIT(0),
7644 .gdscr = 0xc8004,
7645 .en_rest_wait_val = 0x2,
7646 .en_few_wait_val = 0x2,
7647 .clk_dis_wait_val = 0xf,
7656 .gdscr = 0x2e004,
7657 .en_rest_wait_val = 0x2,
7658 .en_few_wait_val = 0x2,
7659 .clk_dis_wait_val = 0xf,
7668 .gdscr = 0xc0004,
7669 .en_rest_wait_val = 0x2,
7670 .en_few_wait_val = 0x2,
7671 .clk_dis_wait_val = 0xf,
7680 .gdscr = 0xdc004,
7681 .en_rest_wait_val = 0x2,
7682 .en_few_wait_val = 0x2,
7683 .clk_dis_wait_val = 0xf,
7692 .gdscr = 0x6c004,
7693 .en_rest_wait_val = 0x2,
7694 .en_few_wait_val = 0x2,
7695 .clk_dis_wait_val = 0x2,
7704 .gdscr = 0x94004,
7705 .en_rest_wait_val = 0x2,
7706 .en_few_wait_val = 0x2,
7707 .clk_dis_wait_val = 0xf,
7716 .gdscr = 0x75004,
7717 .en_rest_wait_val = 0x2,
7718 .en_few_wait_val = 0x2,
7719 .clk_dis_wait_val = 0x2,
7728 .gdscr = 0x88004,
7729 .en_rest_wait_val = 0x2,
7730 .en_few_wait_val = 0x2,
7731 .clk_dis_wait_val = 0xf,
7740 .gdscr = 0xd3004,
7741 .en_rest_wait_val = 0x2,
7742 .en_few_wait_val = 0x2,
7743 .clk_dis_wait_val = 0x2,
7752 .gdscr = 0xc3004,
7753 .en_rest_wait_val = 0x2,
7754 .en_few_wait_val = 0x2,
7755 .clk_dis_wait_val = 0xf,
7764 .gdscr = 0xd2004,
7765 .en_rest_wait_val = 0x2,
7766 .en_few_wait_val = 0x2,
7767 .clk_dis_wait_val = 0x2,
7776 .gdscr = 0x8a004,
7777 .en_rest_wait_val = 0x2,
7778 .en_few_wait_val = 0x2,
7779 .clk_dis_wait_val = 0xf,
7788 .gdscr = 0xd4004,
7789 .en_rest_wait_val = 0x2,
7790 .en_few_wait_val = 0x2,
7791 .clk_dis_wait_val = 0x2,
7800 .gdscr = 0x77008,
7801 .en_rest_wait_val = 0x2,
7802 .en_few_wait_val = 0x2,
7803 .clk_dis_wait_val = 0xf,
7812 .gdscr = 0xbc004,
7813 .en_rest_wait_val = 0x2,
7814 .en_few_wait_val = 0x2,
7815 .clk_dis_wait_val = 0xf,
7824 .gdscr = 0x9a010,
7825 .en_rest_wait_val = 0x2,
7826 .en_few_wait_val = 0x2,
7827 .clk_dis_wait_val = 0xf,
7836 .gdscr = 0x3f01c,
7837 .en_rest_wait_val = 0x2,
7838 .en_few_wait_val = 0x2,
7839 .clk_dis_wait_val = 0xf,
7848 .gdscr = 0xe2010,
7849 .en_rest_wait_val = 0x2,
7850 .en_few_wait_val = 0x2,
7851 .clk_dis_wait_val = 0xf,
7860 .gdscr = 0xe1010,
7861 .en_rest_wait_val = 0x2,
7862 .en_few_wait_val = 0x2,
7863 .clk_dis_wait_val = 0xf,
7872 .gdscr = 0x5400c,
7873 .en_rest_wait_val = 0x2,
7874 .en_few_wait_val = 0x2,
7875 .clk_dis_wait_val = 0x2,
7884 .gdscr = 0x5402c,
7885 .en_rest_wait_val = 0x2,
7886 .en_few_wait_val = 0x2,
7887 .clk_dis_wait_val = 0x2,
7896 .gdscr = 0x2b008,
7897 .en_rest_wait_val = 0x2,
7898 .en_few_wait_val = 0x2,
7899 .clk_dis_wait_val = 0xf,
7908 .gdscr = 0x2d008,
7909 .en_rest_wait_val = 0x2,
7910 .en_few_wait_val = 0x2,
7911 .clk_dis_wait_val = 0xf,
7920 .gdscr = 0xe0008,
7921 .en_rest_wait_val = 0x2,
7922 .en_few_wait_val = 0x2,
7923 .clk_dis_wait_val = 0xf,
7932 .gdscr = 0xdb024,
7933 .en_rest_wait_val = 0x2,
7934 .en_few_wait_val = 0x2,
7935 .clk_dis_wait_val = 0x2,
7944 .gdscr = 0x2c024,
7945 .en_rest_wait_val = 0x2,
7946 .en_few_wait_val = 0x2,
7947 .clk_dis_wait_val = 0x2,
7956 .gdscr = 0xbe024,
7957 .en_rest_wait_val = 0x2,
7958 .en_few_wait_val = 0x2,
7959 .clk_dis_wait_val = 0x2,
8419 [GCC_AV1E_BCR] = { 0x9b028 },
8420 [GCC_CAMERA_BCR] = { 0x26000 },
8421 [GCC_DISPLAY_BCR] = { 0x27000 },
8422 [GCC_EVA_BCR] = { 0x9b000 },
8423 [GCC_GPU_BCR] = { 0x71000 },
8424 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbc2d0 },
8425 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbc2dc },
8426 [GCC_PCIE_0_PHY_BCR] = { 0xbc2d8 },
8427 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbc2e0 },
8428 [GCC_PCIE_0_TUNNEL_BCR] = { 0xc8000 },
8429 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x7f018 },
8430 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x7f024 },
8431 [GCC_PCIE_1_PHY_BCR] = { 0x7f020 },
8432 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x7f028 },
8433 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2e000 },
8434 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x281d0 },
8435 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x281dc },
8436 [GCC_PCIE_2_PHY_BCR] = { 0x281d8 },
8437 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x281e0 },
8438 [GCC_PCIE_2_TUNNEL_BCR] = { 0xc0000 },
8439 [GCC_PCIE_3A_BCR] = { 0xdc000 },
8440 [GCC_PCIE_3A_LINK_DOWN_BCR] = { 0x7b0a0 },
8441 [GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0x7b0ac },
8442 [GCC_PCIE_3A_PHY_BCR] = { 0x6c000 },
8443 [GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0x7b0b0 },
8444 [GCC_PCIE_3B_BCR] = { 0x94000 },
8445 [GCC_PCIE_3B_LINK_DOWN_BCR] = { 0x7a0c0 },
8446 [GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0x7a0cc },
8447 [GCC_PCIE_3B_PHY_BCR] = { 0x75000 },
8448 [GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0x7a0c8 },
8449 [GCC_PCIE_4_BCR] = { 0x88000 },
8450 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0x980c0 },
8451 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x980cc },
8452 [GCC_PCIE_4_PHY_BCR] = { 0xd3000 },
8453 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x980d0 },
8454 [GCC_PCIE_5_BCR] = { 0xc3000 },
8455 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0x850c0 },
8456 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0x850cc },
8457 [GCC_PCIE_5_PHY_BCR] = { 0xd2000 },
8458 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0x850d0 },
8459 [GCC_PCIE_6_BCR] = { 0x8a000 },
8460 [GCC_PCIE_6_LINK_DOWN_BCR] = { 0x3a0b0 },
8461 [GCC_PCIE_6_NOCSR_COM_PHY_BCR] = { 0x3a0bc },
8462 [GCC_PCIE_6_PHY_BCR] = { 0xd4000 },
8463 [GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR] = { 0x3a0c0 },
8464 [GCC_PCIE_NOC_BCR] = { 0xba294 },
8465 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
8466 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
8467 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
8468 [GCC_PCIE_RSCC_BCR] = { 0xb8000 },
8469 [GCC_PDM_BCR] = { 0x33000 },
8470 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 },
8471 [GCC_QUPV3_WRAPPER_1_BCR] = { 0xb3000 },
8472 [GCC_QUPV3_WRAPPER_2_BCR] = { 0xb4000 },
8473 [GCC_QUPV3_WRAPPER_OOB_BCR] = { 0xe7000 },
8474 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0xca000 },
8475 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0xe6000 },
8476 [GCC_QUSB2PHY_PRIM_BCR] = { 0xad024 },
8477 [GCC_QUSB2PHY_SEC_BCR] = { 0xae000 },
8478 [GCC_QUSB2PHY_TERT_BCR] = { 0xc9000 },
8479 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0xe9000 },
8480 [GCC_SDCC2_BCR] = { 0xb0000 },
8481 [GCC_SDCC4_BCR] = { 0xdf000 },
8482 [GCC_TCSR_PCIE_BCR] = { 0x281e4 },
8483 [GCC_UFS_PHY_BCR] = { 0x77004 },
8484 [GCC_USB20_PRIM_BCR] = { 0xbc000 },
8485 [GCC_USB30_MP_BCR] = { 0x9a00c },
8486 [GCC_USB30_PRIM_BCR] = { 0x3f018 },
8487 [GCC_USB30_SEC_BCR] = { 0xe200c },
8488 [GCC_USB30_TERT_BCR] = { 0xe100c },
8489 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x54008 },
8490 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54028 },
8491 [GCC_USB3_PHY_PRIM_BCR] = { 0xdb000 },
8492 [GCC_USB3_PHY_SEC_BCR] = { 0x2c000 },
8493 [GCC_USB3_PHY_TERT_BCR] = { 0xbe000 },
8494 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x54000 },
8495 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54020 },
8496 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0xdb004 },
8497 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2c004 },
8498 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xbe004 },
8499 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x54004 },
8500 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54024 },
8501 [GCC_USB4_0_BCR] = { 0x2b004 },
8502 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0xdb010 },
8503 [GCC_USB4_1_BCR] = { 0x2d004 },
8504 [GCC_USB4_2_BCR] = { 0xe0004 },
8505 [GCC_USB_0_PHY_BCR] = { 0xdb020 },
8506 [GCC_USB_1_PHY_BCR] = { 0x2c020 },
8507 [GCC_USB_2_PHY_BCR] = { 0xbe020 },
8508 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 },
8509 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 },
8510 [GCC_VIDEO_BCR] = { 0x32000 },
8543 0x26004, /* GCC_CAMERA_AHB_CLK */
8544 0x26040, /* GCC_CAMERA_XO_CLK */
8545 0x27004, /* GCC_DISP_AHB_CLK */
8546 0x71004, /* GCC_GPU_CFG_AHB_CLK */
8547 0x32004, /* GCC_VIDEO_AHB_CLK */
8548 0x32058, /* GCC_VIDEO_XO_CLK */
8555 .max_register = 0x1f8ff0,