Lines Matching +full:0 +full:x1740
39 .l_reg = 0x0004,
40 .m_reg = 0x0008,
41 .n_reg = 0x000c,
42 .config_reg = 0x0014,
43 .mode_reg = 0x0000,
44 .status_reg = 0x001c,
57 .enable_reg = 0x1480,
58 .enable_mask = BIT(0),
70 .l_reg = 0x0044,
71 .m_reg = 0x0048,
72 .n_reg = 0x004c,
73 .config_reg = 0x0054,
74 .mode_reg = 0x0040,
75 .status_reg = 0x005c,
88 .enable_reg = 0x1480,
101 .l_reg = 0x1dc4,
102 .m_reg = 0x1dc8,
103 .n_reg = 0x1dcc,
104 .config_reg = 0x1dd4,
105 .mode_reg = 0x1dc0,
106 .status_reg = 0x1ddc,
119 .enable_reg = 0x1480,
132 { P_XO, 0 },
142 { P_XO, 0 },
154 { P_XO, 0 },
164 { P_XO, 0 },
174 { P_XO, 0 },
184 { P_XO, 0 },
194 .cmd_rcgr = 0x0150,
206 .cmd_rcgr = 0x0190,
218 .cmd_rcgr = 0x0120,
230 F(100000000, P_GPLL0, 6, 0, 0),
231 F(200000000, P_GPLL0, 3, 0, 0),
232 F(240000000, P_GPLL0, 2.5, 0, 0),
237 .cmd_rcgr = 0x1d64,
256 .cmd_rcgr = 0x03d4,
275 .cmd_rcgr = 0x1bd4,
294 .cmd_rcgr = 0x1be8,
307 .halt_reg = 0x1bd0,
309 .enable_reg = 0x1bd0,
310 .enable_mask = BIT(0),
324 .halt_reg = 0x1bcc,
326 .enable_reg = 0x1bcc,
327 .enable_mask = BIT(0),
341 F(19200000, P_XO, 1, 0, 0),
342 F(50000000, P_GPLL0, 12, 0, 0),
347 .cmd_rcgr = 0x0660,
361 F(4800000, P_XO, 4, 0, 0),
362 F(9600000, P_XO, 2, 0, 0),
364 F(19200000, P_XO, 1, 0, 0),
366 F(50000000, P_GPLL0, 12, 0, 0),
371 .cmd_rcgr = 0x064c,
385 .cmd_rcgr = 0x06e0,
398 .cmd_rcgr = 0x06cc,
412 .cmd_rcgr = 0x0760,
425 .cmd_rcgr = 0x074c,
439 .cmd_rcgr = 0x07e0,
452 .cmd_rcgr = 0x07cc,
466 .cmd_rcgr = 0x0860,
479 .cmd_rcgr = 0x084c,
493 .cmd_rcgr = 0x08e0,
506 .cmd_rcgr = 0x08cc,
524 F(19200000, P_XO, 1, 0, 0),
527 F(40000000, P_GPLL0, 15, 0, 0),
529 F(48000000, P_GPLL0, 12.5, 0, 0),
533 F(60000000, P_GPLL0, 10, 0, 0),
534 F(63160000, P_GPLL0, 9.5, 0, 0),
539 .cmd_rcgr = 0x068c,
553 .cmd_rcgr = 0x070c,
567 .cmd_rcgr = 0x078c,
581 .cmd_rcgr = 0x080c,
595 .cmd_rcgr = 0x088c,
609 .cmd_rcgr = 0x090c,
623 .cmd_rcgr = 0x09a0,
636 .cmd_rcgr = 0x098c,
650 .cmd_rcgr = 0x0a20,
663 .cmd_rcgr = 0x0a0c,
677 .cmd_rcgr = 0x0aa0,
690 .cmd_rcgr = 0x0a8c,
704 .cmd_rcgr = 0x0b20,
717 .cmd_rcgr = 0x0b0c,
731 .cmd_rcgr = 0x0ba0,
744 .cmd_rcgr = 0x0b8c,
758 .cmd_rcgr = 0x0c20,
771 .cmd_rcgr = 0x0c0c,
785 .cmd_rcgr = 0x09cc,
799 .cmd_rcgr = 0x0a4c,
813 .cmd_rcgr = 0x0acc,
827 .cmd_rcgr = 0x0b4c,
841 .cmd_rcgr = 0x0bcc,
855 .cmd_rcgr = 0x0c4c,
869 F(50000000, P_GPLL0, 12, 0, 0),
870 F(85710000, P_GPLL0, 7, 0, 0),
871 F(100000000, P_GPLL0, 6, 0, 0),
872 F(171430000, P_GPLL0, 3.5, 0, 0),
877 .cmd_rcgr = 0x1050,
890 F(50000000, P_GPLL0, 12, 0, 0),
891 F(85710000, P_GPLL0, 7, 0, 0),
892 F(100000000, P_GPLL0, 6, 0, 0),
893 F(171430000, P_GPLL0, 3.5, 0, 0),
898 .cmd_rcgr = 0x1090,
911 F(50000000, P_GPLL0, 12, 0, 0),
912 F(85710000, P_GPLL0, 7, 0, 0),
913 F(100000000, P_GPLL0, 6, 0, 0),
914 F(171430000, P_GPLL0, 3.5, 0, 0),
919 .cmd_rcgr = 0x1d10,
932 F(19200000, P_XO, 1, 0, 0),
933 F(100000000, P_GPLL0, 6, 0, 0),
934 F(200000000, P_GPLL0, 3, 0, 0),
939 .cmd_rcgr = 0x1904,
953 .cmd_rcgr = 0x1944,
967 .cmd_rcgr = 0x1984,
986 .cmd_rcgr = 0x1b2c,
1000 .cmd_rcgr = 0x1bac,
1014 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
1015 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
1020 .cmd_rcgr = 0x1b18,
1033 .cmd_rcgr = 0x1b98,
1046 F(60000000, P_GPLL0, 10, 0, 0),
1051 .cmd_rcgr = 0x0cd0,
1064 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1065 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1066 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1071 .cmd_rcgr = 0x1c94,
1084 F(19200000, P_XO, 1, 0, 0),
1085 F(50000000, P_GPLL0, 12, 0, 0),
1086 F(100000000, P_GPLL0, 6, 0, 0),
1091 .cmd_rcgr = 0x1c80,
1104 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1105 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1106 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1111 .cmd_rcgr = 0x1ca8,
1124 F(100000000, P_GPLL0, 6, 0, 0),
1129 .cmd_rcgr = 0x1c5c,
1146 F(50000000, P_GPLL0, 12, 0, 0),
1147 F(100000000, P_GPLL0, 6, 0, 0),
1148 F(192000000, P_GPLL4, 4, 0, 0),
1149 F(200000000, P_GPLL0, 3, 0, 0),
1150 F(384000000, P_GPLL4, 2, 0, 0),
1155 .cmd_rcgr = 0x04d0,
1169 .cmd_rcgr = 0x0510,
1183 .cmd_rcgr = 0x0550,
1197 .cmd_rcgr = 0x0590,
1216 .cmd_rcgr = 0x0d90,
1230 F(60000000, P_GPLL0, 10, 0, 0),
1235 .cmd_rcgr = 0x03e8,
1248 F(75000000, P_GPLL0, 8, 0, 0),
1253 .cmd_rcgr = 0x0490,
1266 F(480000000, P_GPLL1, 1, 0, 0),
1271 { P_XO, 0 },
1276 .cmd_rcgr = 0x0440,
1292 F(60000000, P_GPLL1, 8, 0, 0),
1297 .cmd_rcgr = 0x046c,
1314 F(9600000, P_XO, 2, 0, 0),
1319 .cmd_rcgr = 0x0458,
1332 F(60000000, P_GPLL0, 10, 0, 0),
1337 .cmd_rcgr = 0x1f00,
1350 .halt_reg = 0x1f14,
1352 .enable_reg = 0x1f14,
1353 .enable_mask = BIT(0),
1367 F(75000000, P_GPLL0, 8, 0, 0),
1372 .cmd_rcgr = 0x041c,
1385 .enable_reg = 0x1484,
1398 .halt_reg = 0x0d44,
1401 .enable_reg = 0x1484,
1415 .halt_reg = 0x05c4,
1418 .enable_reg = 0x1484,
1432 .halt_reg = 0x0648,
1434 .enable_reg = 0x0648,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0x0644,
1451 .enable_reg = 0x0644,
1452 .enable_mask = BIT(0),
1466 .halt_reg = 0x06c8,
1468 .enable_reg = 0x06c8,
1469 .enable_mask = BIT(0),
1483 .halt_reg = 0x06c4,
1485 .enable_reg = 0x06c4,
1486 .enable_mask = BIT(0),
1500 .halt_reg = 0x0748,
1502 .enable_reg = 0x0748,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x0744,
1519 .enable_reg = 0x0744,
1520 .enable_mask = BIT(0),
1534 .halt_reg = 0x07c8,
1536 .enable_reg = 0x07c8,
1537 .enable_mask = BIT(0),
1551 .halt_reg = 0x07c4,
1553 .enable_reg = 0x07c4,
1554 .enable_mask = BIT(0),
1568 .halt_reg = 0x0848,
1570 .enable_reg = 0x0848,
1571 .enable_mask = BIT(0),
1585 .halt_reg = 0x0844,
1587 .enable_reg = 0x0844,
1588 .enable_mask = BIT(0),
1602 .halt_reg = 0x08c8,
1604 .enable_reg = 0x08c8,
1605 .enable_mask = BIT(0),
1619 .halt_reg = 0x08c4,
1621 .enable_reg = 0x08c4,
1622 .enable_mask = BIT(0),
1636 .halt_reg = 0x0684,
1638 .enable_reg = 0x0684,
1639 .enable_mask = BIT(0),
1653 .halt_reg = 0x0704,
1655 .enable_reg = 0x0704,
1656 .enable_mask = BIT(0),
1670 .halt_reg = 0x0784,
1672 .enable_reg = 0x0784,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0x0804,
1689 .enable_reg = 0x0804,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x0884,
1706 .enable_reg = 0x0884,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x0904,
1723 .enable_reg = 0x0904,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x0944,
1741 .enable_reg = 0x1484,
1755 .halt_reg = 0x0988,
1757 .enable_reg = 0x0988,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x0984,
1774 .enable_reg = 0x0984,
1775 .enable_mask = BIT(0),
1789 .halt_reg = 0x0a08,
1791 .enable_reg = 0x0a08,
1792 .enable_mask = BIT(0),
1806 .halt_reg = 0x0a04,
1808 .enable_reg = 0x0a04,
1809 .enable_mask = BIT(0),
1823 .halt_reg = 0x0a88,
1825 .enable_reg = 0x0a88,
1826 .enable_mask = BIT(0),
1840 .halt_reg = 0x0a84,
1842 .enable_reg = 0x0a84,
1843 .enable_mask = BIT(0),
1857 .halt_reg = 0x0b08,
1859 .enable_reg = 0x0b08,
1860 .enable_mask = BIT(0),
1874 .halt_reg = 0x0b04,
1876 .enable_reg = 0x0b04,
1877 .enable_mask = BIT(0),
1891 .halt_reg = 0x0b88,
1893 .enable_reg = 0x0b88,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x0b84,
1910 .enable_reg = 0x0b84,
1911 .enable_mask = BIT(0),
1925 .halt_reg = 0x0c08,
1927 .enable_reg = 0x0c08,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x0c04,
1944 .enable_reg = 0x0c04,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0x09c4,
1961 .enable_reg = 0x09c4,
1962 .enable_mask = BIT(0),
1976 .halt_reg = 0x0a44,
1978 .enable_reg = 0x0a44,
1979 .enable_mask = BIT(0),
1993 .halt_reg = 0x0ac4,
1995 .enable_reg = 0x0ac4,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0x0b44,
2012 .enable_reg = 0x0b44,
2013 .enable_mask = BIT(0),
2027 .halt_reg = 0x0bc4,
2029 .enable_reg = 0x0bc4,
2030 .enable_mask = BIT(0),
2044 .halt_reg = 0x0c44,
2046 .enable_reg = 0x0c44,
2047 .enable_mask = BIT(0),
2061 .halt_reg = 0x0e04,
2064 .enable_reg = 0x1484,
2078 .halt_reg = 0x104c,
2081 .enable_reg = 0x1484,
2095 .halt_reg = 0x1048,
2098 .enable_reg = 0x1484,
2112 .halt_reg = 0x1050,
2115 .enable_reg = 0x1484,
2130 .halt_reg = 0x108c,
2133 .enable_reg = 0x1484,
2134 .enable_mask = BIT(0),
2147 .halt_reg = 0x1088,
2150 .enable_reg = 0x1484,
2164 .halt_reg = 0x1090,
2167 .enable_reg = 0x1484,
2182 .halt_reg = 0x1d0c,
2185 .enable_reg = 0x1d0c,
2186 .enable_mask = BIT(0),
2199 .halt_reg = 0x1088,
2202 .enable_reg = 0x1d08,
2203 .enable_mask = BIT(0),
2216 .halt_reg = 0x1090,
2219 .enable_reg = 0x1d04,
2220 .enable_mask = BIT(0),
2234 .halt_reg = 0x1900,
2236 .enable_reg = 0x1900,
2237 .enable_mask = BIT(0),
2251 .halt_reg = 0x1940,
2253 .enable_reg = 0x1940,
2254 .enable_mask = BIT(0),
2268 .halt_reg = 0x1980,
2270 .enable_reg = 0x1980,
2271 .enable_mask = BIT(0),
2285 .halt_reg = 0x0248,
2287 .enable_reg = 0x0248,
2288 .enable_mask = BIT(0),
2301 .halt_reg = 0x1b10,
2303 .enable_reg = 0x1b10,
2304 .enable_mask = BIT(0),
2318 .halt_reg = 0x1b0c,
2320 .enable_reg = 0x1b0c,
2321 .enable_mask = BIT(0),
2335 .halt_reg = 0x1b08,
2337 .enable_reg = 0x1b08,
2338 .enable_mask = BIT(0),
2352 .halt_reg = 0x1b14,
2354 .enable_reg = 0x1b14,
2355 .enable_mask = BIT(0),
2369 .halt_reg = 0x1b04,
2371 .enable_reg = 0x1b04,
2372 .enable_mask = BIT(0),
2386 .halt_reg = 0x1b90,
2388 .enable_reg = 0x1b90,
2389 .enable_mask = BIT(0),
2403 .halt_reg = 0x1b8c,
2405 .enable_reg = 0x1b8c,
2406 .enable_mask = BIT(0),
2420 .halt_reg = 0x1b88,
2422 .enable_reg = 0x1b88,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x1b94,
2439 .enable_reg = 0x1b94,
2440 .enable_mask = BIT(0),
2454 .halt_reg = 0x1b84,
2456 .enable_reg = 0x1b84,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x0ccc,
2473 .enable_reg = 0x0ccc,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x0cc4,
2490 .enable_reg = 0x0cc4,
2491 .enable_mask = BIT(0),
2504 .halt_reg = 0x01a4,
2506 .enable_reg = 0x01a4,
2507 .enable_mask = BIT(0),
2521 .halt_reg = 0x0d04,
2524 .enable_reg = 0x1484,
2538 .halt_reg = 0x1c54,
2540 .enable_reg = 0x1c54,
2541 .enable_mask = BIT(0),
2555 .halt_reg = 0x1c44,
2557 .enable_reg = 0x1c44,
2558 .enable_mask = BIT(0),
2572 .halt_reg = 0x1c48,
2574 .enable_reg = 0x1c48,
2575 .enable_mask = BIT(0),
2589 .halt_reg = 0x1c50,
2591 .enable_reg = 0x1c50,
2592 .enable_mask = BIT(0),
2606 .halt_reg = 0x1c58,
2608 .enable_reg = 0x1c58,
2609 .enable_mask = BIT(0),
2623 .halt_reg = 0x1c4c,
2625 .enable_reg = 0x1c4c,
2626 .enable_mask = BIT(0),
2640 .halt_reg = 0x04c8,
2642 .enable_reg = 0x04c8,
2643 .enable_mask = BIT(0),
2656 .halt_reg = 0x04c4,
2658 .enable_reg = 0x04c4,
2659 .enable_mask = BIT(0),
2673 .halt_reg = 0x04e8,
2675 .enable_reg = 0x04e8,
2676 .enable_mask = BIT(0),
2689 .halt_reg = 0x04e4,
2691 .enable_reg = 0x04e4,
2692 .enable_mask = BIT(0),
2705 .halt_reg = 0x0508,
2707 .enable_reg = 0x0508,
2708 .enable_mask = BIT(0),
2721 .halt_reg = 0x0504,
2723 .enable_reg = 0x0504,
2724 .enable_mask = BIT(0),
2738 .halt_reg = 0x0548,
2740 .enable_reg = 0x0548,
2741 .enable_mask = BIT(0),
2754 .halt_reg = 0x0544,
2756 .enable_reg = 0x0544,
2757 .enable_mask = BIT(0),
2771 .halt_reg = 0x0588,
2773 .enable_reg = 0x0588,
2774 .enable_mask = BIT(0),
2787 .halt_reg = 0x0584,
2789 .enable_reg = 0x0584,
2790 .enable_mask = BIT(0),
2804 .halt_reg = 0x013c,
2806 .enable_reg = 0x013c,
2807 .enable_mask = BIT(0),
2821 .halt_reg = 0x0108,
2823 .enable_reg = 0x0108,
2824 .enable_mask = BIT(0),
2838 .halt_reg = 0x0138,
2840 .enable_reg = 0x0138,
2841 .enable_mask = BIT(0),
2855 .halt_reg = 0x0d84,
2857 .enable_reg = 0x0d84,
2858 .enable_mask = BIT(0),
2871 .halt_reg = 0x0d8c,
2873 .enable_reg = 0x0d8c,
2874 .enable_mask = BIT(0),
2888 .halt_reg = 0x0d88,
2890 .enable_reg = 0x0d88,
2891 .enable_mask = BIT(0),
2905 .halt_reg = 0x1d48,
2907 .enable_reg = 0x1d48,
2908 .enable_mask = BIT(0),
2922 .halt_reg = 0x1d44,
2924 .enable_reg = 0x1d44,
2925 .enable_mask = BIT(0),
2939 .halt_reg = 0x1d50,
2941 .enable_reg = 0x1d50,
2942 .enable_mask = BIT(0),
2956 .halt_reg = 0x1d5c,
2958 .enable_reg = 0x1d5c,
2959 .enable_mask = BIT(0),
2973 .halt_reg = 0x1d60,
2975 .enable_reg = 0x1d60,
2976 .enable_mask = BIT(0),
2990 .halt_reg = 0x1d4c,
2992 .enable_reg = 0x1d4c,
2993 .enable_mask = BIT(0),
3007 .halt_reg = 0x1d54,
3009 .enable_reg = 0x1d54,
3010 .enable_mask = BIT(0),
3024 .halt_reg = 0x1d58,
3026 .enable_reg = 0x1d58,
3027 .enable_mask = BIT(0),
3041 .halt_reg = 0x04ac,
3043 .enable_reg = 0x04ac,
3044 .enable_mask = BIT(0),
3057 .halt_reg = 0x04b4,
3059 .enable_reg = 0x04b4,
3060 .enable_mask = BIT(0),
3073 .halt_reg = 0x03c8,
3075 .enable_reg = 0x03c8,
3076 .enable_mask = BIT(0),
3090 .halt_reg = 0x1bc8,
3092 .enable_reg = 0x1bc8,
3093 .enable_mask = BIT(0),
3107 .halt_reg = 0x03d0,
3109 .enable_reg = 0x03d0,
3110 .enable_mask = BIT(0),
3124 .halt_reg = 0x03cc,
3126 .enable_reg = 0x03cc,
3127 .enable_mask = BIT(0),
3140 .halt_reg = 0x0488,
3142 .enable_reg = 0x0488,
3143 .enable_mask = BIT(0),
3156 .halt_reg = 0x048c,
3158 .enable_reg = 0x048c,
3159 .enable_mask = BIT(0),
3173 .halt_reg = 0x0484,
3175 .enable_reg = 0x0484,
3176 .enable_mask = BIT(0),
3190 .halt_reg = 0x0408,
3192 .enable_reg = 0x0408,
3193 .enable_mask = BIT(0),
3206 .halt_reg = 0x0410,
3208 .enable_reg = 0x0410,
3209 .enable_mask = BIT(0),
3223 .halt_reg = 0x0414,
3225 .enable_reg = 0x0414,
3226 .enable_mask = BIT(0),
3240 .halt_reg = 0x0418,
3242 .enable_reg = 0x0418,
3243 .enable_mask = BIT(0),
3256 .halt_reg = 0x040c,
3258 .enable_reg = 0x040c,
3259 .enable_mask = BIT(0),
3273 .gdscr = 0x404,
3281 .gdscr = 0x1ac4,
3289 .gdscr = 0x1b44,
3297 .gdscr = 0x1e84,
3506 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3507 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3508 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3509 [GCC_IMEM_BCR] = { 0x0200 },
3510 [GCC_MMSS_BCR] = { 0x0240 },
3511 [GCC_QDSS_BCR] = { 0x0300 },
3512 [GCC_USB_30_BCR] = { 0x03c0 },
3513 [GCC_USB3_PHY_BCR] = { 0x03fc },
3514 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3515 [GCC_USB_HS_BCR] = { 0x0480 },
3516 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3517 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3518 [GCC_SDCC1_BCR] = { 0x04c0 },
3519 [GCC_SDCC2_BCR] = { 0x0500 },
3520 [GCC_SDCC3_BCR] = { 0x0540 },
3521 [GCC_SDCC4_BCR] = { 0x0580 },
3522 [GCC_BLSP1_BCR] = { 0x05c0 },
3523 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3524 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3525 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3526 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3527 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3528 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3529 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3530 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3531 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3532 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3533 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3534 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3535 [GCC_BLSP2_BCR] = { 0x0940 },
3536 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3537 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3538 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3539 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3540 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3541 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3542 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3543 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3544 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3545 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3546 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3547 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3548 [GCC_PDM_BCR] = { 0x0cc0 },
3549 [GCC_PRNG_BCR] = { 0x0d00 },
3550 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3551 [GCC_TSIF_BCR] = { 0x0d80 },
3552 [GCC_TCSR_BCR] = { 0x0dc0 },
3553 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3554 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3555 [GCC_TLMM_BCR] = { 0x0e80 },
3556 [GCC_MPM_BCR] = { 0x0ec0 },
3557 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3558 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3559 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3560 [GCC_SPMI_BCR] = { 0x0fc0 },
3561 [GCC_SPDM_BCR] = { 0x1000 },
3562 [GCC_CE1_BCR] = { 0x1040 },
3563 [GCC_CE2_BCR] = { 0x1080 },
3564 [GCC_BIMC_BCR] = { 0x1100 },
3565 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3566 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3567 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3568 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3569 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3570 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3571 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3572 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3573 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3574 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3575 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3576 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3577 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3578 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3579 [GCC_DEHR_BCR] = { 0x1300 },
3580 [GCC_RBCPR_BCR] = { 0x1380 },
3581 [GCC_MSS_RESTART] = { 0x1680 },
3582 [GCC_LPASS_RESTART] = { 0x16c0 },
3583 [GCC_WCSS_RESTART] = { 0x1700 },
3584 [GCC_VENUS_RESTART] = { 0x1740 },
3585 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3586 [GCC_SPSS_BCR] = { 0x1a80 },
3587 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3588 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3589 [GCC_PCIE_1_BCR] = { 0x1b40 },
3590 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3591 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3592 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3593 [GCC_SATA_BCR] = { 0x1c40 },
3594 [GCC_CE3_BCR] = { 0x1d00 },
3595 [GCC_UFS_BCR] = { 0x1d40 },
3596 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3603 .max_register = 0x1fc0,