Lines Matching +full:0 +full:x1020

40 	{ 249600000, 2000000000, 0 },
45 .l = 0x20,
46 .alpha = 0x800,
47 .config_ctl_val = 0x20485699,
48 .config_ctl_hi_val = 0x00002261,
49 .config_ctl_hi1_val = 0x329a299c,
50 .user_ctl_val = 0x00000001,
51 .user_ctl_hi_val = 0x00000805,
52 .user_ctl_hi1_val = 0x00000000,
56 .offset = 0x0,
73 { P_BI_TCXO, 0 },
83 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
117 { P_BI_TCXO, 0 },
125 F(19200000, P_BI_TCXO, 1, 0, 0),
126 F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
127 F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
132 .cmd_rcgr = 0x115c,
133 .mnd_width = 0,
146 .cmd_rcgr = 0x10c4,
147 .mnd_width = 0,
160 F(19200000, P_BI_TCXO, 1, 0, 0),
165 .cmd_rcgr = 0x10e0,
166 .mnd_width = 0,
179 F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
180 F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
181 F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
182 F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
183 F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
188 .cmd_rcgr = 0x107c,
189 .mnd_width = 0,
203 .cmd_rcgr = 0x1064,
217 F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
218 F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
223 .cmd_rcgr = 0x1094,
224 .mnd_width = 0,
237 .cmd_rcgr = 0x10ac,
238 .mnd_width = 0,
251 .reg = 0x10dc,
252 .shift = 0,
265 .halt_reg = 0x104c,
268 .enable_reg = 0x104c,
269 .enable_mask = BIT(0),
283 .halt_reg = 0x102c,
286 .enable_reg = 0x102c,
287 .enable_mask = BIT(0),
301 .halt_reg = 0x1030,
304 .enable_reg = 0x1030,
305 .enable_mask = BIT(0),
319 .halt_reg = 0x1034,
322 .enable_reg = 0x1034,
323 .enable_mask = BIT(0),
337 .halt_reg = 0x1010,
340 .enable_reg = 0x1010,
341 .enable_mask = BIT(0),
355 .halt_reg = 0x1020,
358 .enable_reg = 0x1020,
359 .enable_mask = BIT(0),
373 .halt_reg = 0x2004,
376 .enable_reg = 0x2004,
377 .enable_mask = BIT(0),
391 .halt_reg = 0x1168,
394 .enable_reg = 0x1168,
395 .enable_mask = BIT(0),
409 .halt_reg = 0x1018,
412 .enable_reg = 0x1018,
413 .enable_mask = BIT(0),
427 .halt_reg = 0x200c,
430 .enable_reg = 0x200c,
431 .enable_mask = BIT(0),
445 .halt_reg = 0x2008,
448 .enable_reg = 0x2008,
449 .enable_mask = BIT(0),
463 .halt_reg = 0x1028,
466 .enable_reg = 0x1028,
467 .enable_mask = BIT(0),
483 .enable_reg = 0x5004,
484 .enable_mask = BIT(0),
496 .enable_reg = 0x5008,
497 .enable_mask = BIT(0),
507 .gdscr = 0x1004,
508 .en_rest_wait_val = 0x2,
509 .en_few_wait_val = 0x2,
510 .clk_dis_wait_val = 0xf,
545 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
546 [DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
557 .max_register = 0x10000,