Lines Matching +full:0 +full:x8004
41 #define DISP_CC_MISC_CMD 0xF000
56 { 249600000, 2300000000, 0 },
61 .l = 0xd,
62 .alpha = 0x6492,
63 .config_ctl_val = 0x20485699,
64 .config_ctl_hi_val = 0x00182261,
65 .config_ctl_hi1_val = 0x82aa299c,
66 .test_ctl_val = 0x00000000,
67 .test_ctl_hi_val = 0x00000003,
68 .test_ctl_hi1_val = 0x00009000,
69 .test_ctl_hi2_val = 0x00000034,
70 .user_ctl_val = 0x00000000,
71 .user_ctl_hi_val = 0x00000005,
75 .offset = 0x0,
93 { P_BI_TCXO, 0 },
101 { P_BI_TCXO, 0 },
113 { P_BI_TCXO, 0 },
125 { P_BI_TCXO, 0 },
135 { P_BI_TCXO, 0 },
145 { P_BI_TCXO, 0 },
155 { P_BI_TCXO, 0 },
169 { P_SLEEP_CLK, 0 },
177 F(19200000, P_BI_TCXO, 1, 0, 0),
178 F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
179 F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
184 .cmd_rcgr = 0x8130,
185 .mnd_width = 0,
199 .cmd_rcgr = 0x8098,
200 .mnd_width = 0,
213 F(19200000, P_BI_TCXO, 1, 0, 0),
218 .cmd_rcgr = 0x8118,
219 .mnd_width = 0,
233 .cmd_rcgr = 0x80cc,
234 .mnd_width = 0,
247 .cmd_rcgr = 0x80e8,
261 .cmd_rcgr = 0x8100,
275 F(9600000, P_BI_TCXO, 2, 0, 0),
276 F(12800000, P_BI_TCXO, 1.5, 0, 0),
277 F(19200000, P_BI_TCXO, 1, 0, 0),
281 .cmd_rcgr = 0x80b4,
282 .mnd_width = 0,
296 F(19200000, P_BI_TCXO, 1, 0, 0),
297 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
298 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
299 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
300 F(342000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
301 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
302 F(535000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
303 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
304 F(630000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
309 .cmd_rcgr = 0x8068,
310 .mnd_width = 0,
324 .cmd_rcgr = 0x8050,
338 .cmd_rcgr = 0x8080,
339 .mnd_width = 0,
353 F(32000, P_SLEEP_CLK, 1, 0, 0),
358 .cmd_rcgr = 0xe054,
359 .mnd_width = 0,
373 .cmd_rcgr = 0xe034,
374 .mnd_width = 0,
388 .reg = 0x80b0,
389 .shift = 0,
403 .reg = 0x80e4,
404 .shift = 0,
418 .halt_reg = 0xe050,
421 .enable_reg = 0xe050,
422 .enable_mask = BIT(0),
436 .halt_reg = 0xa020,
439 .enable_reg = 0xa020,
440 .enable_mask = BIT(0),
454 .halt_reg = 0x804c,
457 .enable_reg = 0x804c,
458 .enable_mask = BIT(0),
472 .halt_reg = 0x8024,
475 .enable_reg = 0x8024,
476 .enable_mask = BIT(0),
490 .halt_reg = 0x8028,
493 .enable_reg = 0x8028,
494 .enable_mask = BIT(0),
508 .halt_reg = 0x8048,
511 .enable_reg = 0x8048,
512 .enable_mask = BIT(0),
526 .halt_reg = 0x803c,
529 .enable_reg = 0x803c,
530 .enable_mask = BIT(0),
544 .halt_reg = 0x8030,
547 .enable_reg = 0x8030,
548 .enable_mask = BIT(0),
562 .halt_reg = 0x8038,
565 .enable_reg = 0x8038,
566 .enable_mask = BIT(0),
580 .halt_reg = 0x8040,
583 .enable_reg = 0x8040,
584 .enable_mask = BIT(0),
598 .halt_reg = 0x8044,
601 .enable_reg = 0x8044,
602 .enable_mask = BIT(0),
616 .halt_reg = 0x8034,
619 .enable_reg = 0x8034,
620 .enable_mask = BIT(0),
634 .halt_reg = 0x802c,
637 .enable_reg = 0x802c,
638 .enable_mask = BIT(0),
652 .halt_reg = 0xa004,
655 .enable_reg = 0xa004,
656 .enable_mask = BIT(0),
670 .halt_reg = 0x8008,
673 .enable_reg = 0x8008,
674 .enable_mask = BIT(0),
688 .halt_reg = 0xa010,
691 .enable_reg = 0xa010,
692 .enable_mask = BIT(0),
706 .halt_reg = 0x8014,
709 .enable_reg = 0x8014,
710 .enable_mask = BIT(0),
724 .halt_reg = 0xc004,
727 .enable_reg = 0xc004,
728 .enable_mask = BIT(0),
742 .halt_reg = 0x8004,
745 .enable_reg = 0x8004,
746 .enable_mask = BIT(0),
760 .halt_reg = 0xc00c,
763 .enable_reg = 0xc00c,
764 .enable_mask = BIT(0),
778 .halt_reg = 0xc008,
781 .enable_reg = 0xc008,
782 .enable_mask = BIT(0),
796 .halt_reg = 0xa01c,
799 .enable_reg = 0xa01c,
800 .enable_mask = BIT(0),
814 .halt_reg = 0x8020,
817 .enable_reg = 0x8020,
818 .enable_mask = BIT(0),
832 .gdscr = 0x9000,
833 .en_rest_wait_val = 0x2,
834 .en_few_wait_val = 0x2,
835 .clk_dis_wait_val = 0xf,
844 .gdscr = 0xb000,
845 .en_rest_wait_val = 0x2,
846 .en_few_wait_val = 0x2,
847 .clk_dis_wait_val = 0xf,
898 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
899 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
900 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
913 0xe06c, /* DISP_CC_SLEEP_CLK */
914 0xe04c, /* DISP_CC_XO_CLK */
921 .max_register = 0x11008,
928 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); in disp_cc_milos_clk_regs_configure()