Lines Matching +full:sdm660 +full:- +full:bimc
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
17 #include <linux/soc/qcom/smd-rpm.h>
19 #include <dt-bindings/clock/qcom,rpmcc.h>
194 .key = cpu_to_le32(r->rpm_key),
196 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
200 r->rpm_res_type, r->rpm_clk_id, &req,
205 r->rpm_res_type, r->rpm_clk_id, &req,
217 .key = cpu_to_le32(r->rpm_key),
223 r->rpm_res_type, r->rpm_clk_id, &req,
231 .key = cpu_to_le32(r->rpm_key),
237 r->rpm_res_type, r->rpm_clk_id, &req,
247 * Active-only clocks don't care what the rate is during sleep. So,
250 if (r->active_only)
259 struct clk_smd_rpm *peer = r->peer;
268 if (!r->rate)
271 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
274 if (peer->enabled)
275 to_active_sleep(peer, peer->rate,
280 if (r->branch)
288 if (r->branch)
298 r->enabled = true;
308 struct clk_smd_rpm *peer = r->peer;
315 if (!r->rate)
319 if (peer->enabled)
320 to_active_sleep(peer, peer->rate, &peer_rate,
323 active_rate = r->branch ? !!peer_rate : peer_rate;
328 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
333 r->enabled = false;
340 struct clk_smd_rpm *peer = r->peer;
348 if (!r->enabled)
354 if (peer->enabled)
355 to_active_sleep(peer, peer->rate,
368 r->rate = rate;
394 return r->rate;
463 DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0);
1262 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1263 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1264 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
1265 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1266 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 },
1267 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1268 { .compatible = "qcom,rpmcc-msm8937", .data = &rpm_clk_msm8937 },
1269 { .compatible = "qcom,rpmcc-msm8940", .data = &rpm_clk_msm8940 },
1270 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1271 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1272 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1273 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1274 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1275 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1276 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1277 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1278 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
1279 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
1280 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
1281 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
1282 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 },
1291 unsigned int idx = clkspec->args[0];
1293 if (idx >= desc->num_clks) {
1295 return ERR_PTR(-EINVAL);
1298 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1316 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
1318 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1319 return -ENODEV;
1322 desc = of_device_get_match_data(&pdev->dev);
1324 return -EINVAL;
1326 rpm_smd_clks = desc->clks;
1327 num_clks = desc->num_clks;
1329 if (desc->scaling_before_handover) {
1344 for (i = 0; i < desc->num_icc_clks; i++) {
1345 if (!desc->icc_clks[i])
1348 ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
1353 if (!desc->scaling_before_handover) {
1363 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1368 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1373 icc_pdev = platform_device_register_data(pdev->dev.parent,
1374 "icc_smd_rpm", -1, NULL, 0);
1376 dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n",
1380 ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc,
1388 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1394 .name = "qcom-clk-smd-rpm",
1414 MODULE_ALIAS("platform:qcom-clk-smd-rpm");