Lines Matching +full:m +full:- +full:num
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
23 #include "clk-rcg.h"
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
73 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
90 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
104 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
118 struct clk_hw *hw = &rcg->clkr.hw; in update_config()
121 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in update_config()
127 for (count = 500; count > 0; count--) { in update_config()
128 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in update_config()
137 return -EBUSY; in update_config()
144 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_rcg2_set_parent()
146 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), in clk_rcg2_set_parent()
155 * convert_to_reg_val() - Convert divisor values to hardware values.
157 * @f: Frequency table with pure m/n/pre_div parameters.
161 f->pre_div *= 2; in convert_to_reg_val()
162 f->pre_div -= 1; in convert_to_reg_val()
166 * calc_rate() - Calculate rate based on m/n:d values
169 * @m: Multiplier.
171 * @mode: Use zero to ignore m/n calculation.
177 * parent_rate m
178 * rate = ----------- x ---
182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) in calc_rate() argument
188 rate = mult_frac(rate, m, n); in calc_rate()
197 u32 hid_div, m = 0, n = 0, mode = 0, mask; in __clk_rcg2_recalc_rate() local
199 if (rcg->mnd_width) { in __clk_rcg2_recalc_rate()
200 mask = BIT(rcg->mnd_width) - 1; in __clk_rcg2_recalc_rate()
201 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in __clk_rcg2_recalc_rate()
202 m &= mask; in __clk_rcg2_recalc_rate()
203 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); in __clk_rcg2_recalc_rate()
206 n += m; in __clk_rcg2_recalc_rate()
211 mask = BIT(rcg->hid_width) - 1; in __clk_rcg2_recalc_rate()
215 return calc_rate(parent_rate, m, n, mode, hid_div); in __clk_rcg2_recalc_rate()
224 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_recalc_rate()
233 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate()
246 return -EINVAL; in _freq_tbl_determine_rate()
250 return -EINVAL; in _freq_tbl_determine_rate()
252 index = qcom_find_src_index(hw, rcg->parent_map, f->src); in _freq_tbl_determine_rate()
259 return -EINVAL; in _freq_tbl_determine_rate()
262 rate = f->freq; in _freq_tbl_determine_rate()
263 if (f->pre_div) { in _freq_tbl_determine_rate()
265 rate = req->rate; in _freq_tbl_determine_rate()
267 rate *= f->pre_div + 1; in _freq_tbl_determine_rate()
270 if (f->n) { in _freq_tbl_determine_rate()
272 tmp = tmp * f->n; in _freq_tbl_determine_rate()
273 do_div(tmp, f->m); in _freq_tbl_determine_rate()
279 req->best_parent_hw = p; in _freq_tbl_determine_rate()
280 req->best_parent_rate = rate; in _freq_tbl_determine_rate()
281 req->rate = f->freq; in _freq_tbl_determine_rate()
299 if (f->num_confs == 1) { in __clk_rcg2_select_conf()
300 best_conf = f->confs; in __clk_rcg2_select_conf()
305 for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) { in __clk_rcg2_select_conf()
306 index = qcom_find_src_index(hw, rcg->parent_map, conf->src); in __clk_rcg2_select_conf()
315 rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div); in __clk_rcg2_select_conf()
336 return ERR_PTR(-EINVAL); in __clk_rcg2_select_conf()
346 unsigned long clk_flags, rate = req->rate; in _freq_tbl_fm_determine_rate()
353 if (!f || !f->confs) in _freq_tbl_fm_determine_rate()
354 return -EINVAL; in _freq_tbl_fm_determine_rate()
359 index = qcom_find_src_index(hw, rcg->parent_map, conf->src); in _freq_tbl_fm_determine_rate()
366 return -EINVAL; in _freq_tbl_fm_determine_rate()
369 rate = f->freq; in _freq_tbl_fm_determine_rate()
370 if (conf->pre_div) { in _freq_tbl_fm_determine_rate()
372 rate = req->rate; in _freq_tbl_fm_determine_rate()
374 rate *= conf->pre_div + 1; in _freq_tbl_fm_determine_rate()
377 if (conf->n) { in _freq_tbl_fm_determine_rate()
380 tmp = tmp * conf->n; in _freq_tbl_fm_determine_rate()
381 do_div(tmp, conf->m); in _freq_tbl_fm_determine_rate()
388 req->best_parent_hw = p; in _freq_tbl_fm_determine_rate()
389 req->best_parent_rate = rate; in _freq_tbl_fm_determine_rate()
390 req->rate = f->freq; in _freq_tbl_fm_determine_rate()
400 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); in clk_rcg2_determine_rate()
408 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); in clk_rcg2_determine_floor_rate()
416 return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req); in clk_rcg2_fm_determine_rate()
420 * clk_rcg2_split_div() - Split multiplier that doesn't fit in n neither in pre_div.
440 u16 m, n = 1, n_candidate = 1, n_max; in clk_rcg2_calc_mnd() local
443 m = div64_u64(rate, rates_gcd); in clk_rcg2_calc_mnd()
445 while (scaled_parent_rate > (mnd_max + m) * pre_div_max) { in clk_rcg2_calc_mnd()
447 if (m > 1) { in clk_rcg2_calc_mnd()
448 m--; in clk_rcg2_calc_mnd()
449 scaled_parent_rate = mult_frac(scaled_parent_rate, m, (m + 1)); in clk_rcg2_calc_mnd()
452 f->n = mnd_max + m; in clk_rcg2_calc_mnd()
453 f->pre_div = pre_div_max; in clk_rcg2_calc_mnd()
454 f->m = m; in clk_rcg2_calc_mnd()
459 n_max = m + mnd_max; in clk_rcg2_calc_mnd()
476 f->m = m; in clk_rcg2_calc_mnd()
477 f->n = n; in clk_rcg2_calc_mnd()
478 f->pre_div = pre_div > 1 ? pre_div : 0; in clk_rcg2_calc_mnd()
486 int mnd_max = BIT(rcg->mnd_width) - 1; in clk_rcg2_determine_gp_rate()
487 int hid_max = BIT(rcg->hid_width) - 1; in clk_rcg2_determine_gp_rate()
492 parent_rate = clk_get_rate(parent->clk); in clk_rcg2_determine_gp_rate()
494 return -EINVAL; in clk_rcg2_determine_gp_rate()
496 clk_rcg2_calc_mnd(parent_rate, req->rate, f, mnd_max, hid_max / 2); in clk_rcg2_determine_gp_rate()
498 req->rate = calc_rate(parent_rate, f->m, f->n, f->n, f->pre_div); in clk_rcg2_determine_gp_rate()
505 struct clk_hw *hw = &rcg->clkr.hw; in __clk_rcg2_configure_parent()
506 int index = qcom_find_src_index(hw, rcg->parent_map, src); in __clk_rcg2_configure_parent()
512 *_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in __clk_rcg2_configure_parent()
523 if (rcg->mnd_width && f->n) { in __clk_rcg2_configure_mnd()
524 mask = BIT(rcg->mnd_width) - 1; in __clk_rcg2_configure_mnd()
525 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
526 RCG_M_OFFSET(rcg), mask, f->m); in __clk_rcg2_configure_mnd()
530 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
531 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); in __clk_rcg2_configure_mnd()
536 d_val = f->n; in __clk_rcg2_configure_mnd()
538 n_minus_m = f->n - f->m; in __clk_rcg2_configure_mnd()
541 d_val = clamp_t(u32, d_val, f->m, n_minus_m); in __clk_rcg2_configure_mnd()
544 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure_mnd()
550 mask = BIT(rcg->hid_width) - 1; in __clk_rcg2_configure_mnd()
552 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; in __clk_rcg2_configure_mnd()
553 if (rcg->mnd_width && f->n && (f->m != f->n)) in __clk_rcg2_configure_mnd()
555 if (rcg->hw_clk_ctrl) in __clk_rcg2_configure_mnd()
569 ret = __clk_rcg2_configure_parent(rcg, f->src, _cfg); in __clk_rcg2_configure()
585 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_configure()
593 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg); in clk_rcg2_configure()
605 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_configure_gp()
613 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg); in clk_rcg2_configure_gp()
628 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
631 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
634 return -EINVAL; in __clk_rcg2_set_rate()
638 return -EINVAL; in __clk_rcg2_set_rate()
650 f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate); in __clk_rcg2_fm_set_rate()
651 if (!f || !f->confs) in __clk_rcg2_fm_set_rate()
652 return -EINVAL; in __clk_rcg2_fm_set_rate()
658 f_tbl.freq = f->freq; in __clk_rcg2_fm_set_rate()
659 f_tbl.src = conf->src; in __clk_rcg2_fm_set_rate()
660 f_tbl.pre_div = conf->pre_div; in __clk_rcg2_fm_set_rate()
661 f_tbl.m = conf->m; in __clk_rcg2_fm_set_rate()
662 f_tbl.n = conf->n; in __clk_rcg2_fm_set_rate()
677 int mnd_max = BIT(rcg->mnd_width) - 1; in clk_rcg2_set_gp_rate()
678 int hid_max = BIT(rcg->hid_width) - 1; in clk_rcg2_set_gp_rate()
722 u32 notn_m, n, m, d, not2d, mask; in clk_rcg2_get_duty_cycle() local
724 if (!rcg->mnd_width) { in clk_rcg2_get_duty_cycle()
725 /* 50 % duty-cycle for Non-MND RCGs */ in clk_rcg2_get_duty_cycle()
726 duty->num = 1; in clk_rcg2_get_duty_cycle()
727 duty->den = 2; in clk_rcg2_get_duty_cycle()
731 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d); in clk_rcg2_get_duty_cycle()
732 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in clk_rcg2_get_duty_cycle()
733 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); in clk_rcg2_get_duty_cycle()
735 if (!not2d && !m && !notn_m) { in clk_rcg2_get_duty_cycle()
736 /* 50 % duty-cycle always */ in clk_rcg2_get_duty_cycle()
737 duty->num = 1; in clk_rcg2_get_duty_cycle()
738 duty->den = 2; in clk_rcg2_get_duty_cycle()
742 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_get_duty_cycle()
747 n = (~(notn_m) + m) & mask; in clk_rcg2_get_duty_cycle()
749 duty->num = d; in clk_rcg2_get_duty_cycle()
750 duty->den = n; in clk_rcg2_get_duty_cycle()
758 u32 notn_m, n, m, d, not2d, mask, duty_per, cfg; in clk_rcg2_set_duty_cycle() local
761 /* Duty-cycle cannot be modified for non-MND RCGs */ in clk_rcg2_set_duty_cycle()
762 if (!rcg->mnd_width) in clk_rcg2_set_duty_cycle()
763 return -EINVAL; in clk_rcg2_set_duty_cycle()
765 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_set_duty_cycle()
767 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); in clk_rcg2_set_duty_cycle()
768 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in clk_rcg2_set_duty_cycle()
769 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_set_duty_cycle()
771 /* Duty-cycle cannot be modified if MND divider is in bypass mode. */ in clk_rcg2_set_duty_cycle()
773 return -EINVAL; in clk_rcg2_set_duty_cycle()
775 n = (~(notn_m) + m) & mask; in clk_rcg2_set_duty_cycle()
777 duty_per = (duty->num * 100) / duty->den; in clk_rcg2_set_duty_cycle()
788 if ((d / 2) > (n - m)) in clk_rcg2_set_duty_cycle()
789 d = (n - m) * 2; in clk_rcg2_set_duty_cycle()
790 else if ((d / 2) < (m / 2)) in clk_rcg2_set_duty_cycle()
791 d = m; in clk_rcg2_set_duty_cycle()
795 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask, in clk_rcg2_set_duty_cycle()
862 int num; member
866 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
867 { 52, 295 }, /* 119 M */
868 { 11, 57 }, /* 130.25 M */
869 { 63, 307 }, /* 138.50 M */
870 { 11, 50 }, /* 148.50 M */
871 { 47, 206 }, /* 154 M */
872 { 31, 100 }, /* 205.25 M */
873 { 107, 269 }, /* 268.50 M */
877 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
878 { 31, 211 }, /* 119 M */
879 { 32, 199 }, /* 130.25 M */
880 { 63, 307 }, /* 138.50 M */
881 { 11, 60 }, /* 148.50 M */
882 { 50, 263 }, /* 154 M */
883 { 31, 120 }, /* 205.25 M */
884 { 119, 359 }, /* 268.50 M */
892 struct freq_tbl f = *rcg->freq_tbl; in clk_edp_pixel_set_rate()
897 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_set_rate()
905 for (; frac->num; frac++) { in clk_edp_pixel_set_rate()
907 request *= frac->den; in clk_edp_pixel_set_rate()
908 request = div_s64(request, frac->num); in clk_edp_pixel_set_rate()
909 if ((src_rate < (request - delta)) || in clk_edp_pixel_set_rate()
913 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_set_rate()
918 f.m = frac->num; in clk_edp_pixel_set_rate()
919 f.n = frac->den; in clk_edp_pixel_set_rate()
924 return -EINVAL; in clk_edp_pixel_set_rate()
938 const struct freq_tbl *f = rcg->freq_tbl; in clk_edp_pixel_determine_rate()
942 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_determine_rate()
944 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_edp_pixel_determine_rate()
947 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); in clk_edp_pixel_determine_rate()
948 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); in clk_edp_pixel_determine_rate()
950 if (req->best_parent_rate == 810000000) in clk_edp_pixel_determine_rate()
955 for (; frac->num; frac++) { in clk_edp_pixel_determine_rate()
956 request = req->rate; in clk_edp_pixel_determine_rate()
957 request *= frac->den; in clk_edp_pixel_determine_rate()
958 request = div_s64(request, frac->num); in clk_edp_pixel_determine_rate()
959 if ((req->best_parent_rate < (request - delta)) || in clk_edp_pixel_determine_rate()
960 (req->best_parent_rate > (request + delta))) in clk_edp_pixel_determine_rate()
963 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_determine_rate()
968 req->rate = calc_rate(req->best_parent_rate, in clk_edp_pixel_determine_rate()
969 frac->num, frac->den, in clk_edp_pixel_determine_rate()
970 !!frac->den, hid_div); in clk_edp_pixel_determine_rate()
974 return -EINVAL; in clk_edp_pixel_determine_rate()
992 const struct freq_tbl *f = rcg->freq_tbl; in clk_byte_determine_rate()
993 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_byte_determine_rate()
995 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_determine_rate()
998 if (req->rate == 0) in clk_byte_determine_rate()
999 return -EINVAL; in clk_byte_determine_rate()
1001 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); in clk_byte_determine_rate()
1002 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); in clk_byte_determine_rate()
1004 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; in clk_byte_determine_rate()
1007 req->rate = calc_rate(parent_rate, 0, 0, 0, div); in clk_byte_determine_rate()
1016 struct freq_tbl f = *rcg->freq_tbl; in clk_byte_set_rate()
1018 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_set_rate()
1020 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; in clk_byte_set_rate()
1051 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_determine_rate()
1053 unsigned long rate = req->rate; in clk_byte2_determine_rate()
1056 return -EINVAL; in clk_byte2_determine_rate()
1058 p = req->best_parent_hw; in clk_byte2_determine_rate()
1059 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate); in clk_byte2_determine_rate()
1061 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; in clk_byte2_determine_rate()
1064 req->rate = calc_rate(parent_rate, 0, 0, 0, div); in clk_byte2_determine_rate()
1076 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_set_rate()
1079 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; in clk_byte2_set_rate()
1084 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_byte2_set_rate()
1089 if (cfg == rcg->parent_map[i].cfg) { in clk_byte2_set_rate()
1090 f.src = rcg->parent_map[i].src; in clk_byte2_set_rate()
1095 return -EINVAL; in clk_byte2_set_rate()
1132 for (; frac->num; frac++) { in clk_pixel_determine_rate()
1133 request = (req->rate * frac->den) / frac->num; in clk_pixel_determine_rate()
1135 src_rate = clk_hw_round_rate(req->best_parent_hw, request); in clk_pixel_determine_rate()
1136 if ((src_rate < (request - delta)) || in clk_pixel_determine_rate()
1140 req->best_parent_rate = src_rate; in clk_pixel_determine_rate()
1141 req->rate = (src_rate * frac->num) / frac->den; in clk_pixel_determine_rate()
1145 return -EINVAL; in clk_pixel_determine_rate()
1156 u32 mask = BIT(rcg->hid_width) - 1; in clk_pixel_set_rate()
1160 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_pixel_set_rate()
1165 if (cfg == rcg->parent_map[i].cfg) { in clk_pixel_set_rate()
1166 f.src = rcg->parent_map[i].src; in clk_pixel_set_rate()
1170 for (; frac->num; frac++) { in clk_pixel_set_rate()
1171 request = (rate * frac->den) / frac->num; in clk_pixel_set_rate()
1173 if ((parent_rate < (request - delta)) || in clk_pixel_set_rate()
1177 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_pixel_set_rate()
1182 f.m = frac->num; in clk_pixel_set_rate()
1183 f.n = frac->den; in clk_pixel_set_rate()
1187 return -EINVAL; in clk_pixel_set_rate()
1214 u8 mux_div = cgfx->div; in clk_gfx3d_determine_rate()
1217 p0 = cgfx->hws[0]; in clk_gfx3d_determine_rate()
1218 p1 = cgfx->hws[1]; in clk_gfx3d_determine_rate()
1219 p2 = cgfx->hws[2]; in clk_gfx3d_determine_rate()
1221 * This function does ping-pong the RCG between PLLs: if we don't in clk_gfx3d_determine_rate()
1226 return -EINVAL; in clk_gfx3d_determine_rate()
1229 if (req->rate == clk_hw_get_rate(xo)) { in clk_gfx3d_determine_rate()
1230 req->best_parent_hw = xo; in clk_gfx3d_determine_rate()
1237 parent_req.rate = req->rate * mux_div; in clk_gfx3d_determine_rate()
1243 req->rate = req->best_parent_rate = p0_rate; in clk_gfx3d_determine_rate()
1244 req->best_parent_hw = p0; in clk_gfx3d_determine_rate()
1248 if (req->best_parent_hw == p0) { in clk_gfx3d_determine_rate()
1251 req->best_parent_hw = p2; in clk_gfx3d_determine_rate()
1253 req->best_parent_hw = p1; in clk_gfx3d_determine_rate()
1254 } else if (req->best_parent_hw == p2) { in clk_gfx3d_determine_rate()
1255 req->best_parent_hw = p1; in clk_gfx3d_determine_rate()
1257 req->best_parent_hw = p2; in clk_gfx3d_determine_rate()
1260 clk_hw_get_rate_range(req->best_parent_hw, in clk_gfx3d_determine_rate()
1263 if (req->min_rate > parent_req.min_rate) in clk_gfx3d_determine_rate()
1264 parent_req.min_rate = req->min_rate; in clk_gfx3d_determine_rate()
1266 if (req->max_rate < parent_req.max_rate) in clk_gfx3d_determine_rate()
1267 parent_req.max_rate = req->max_rate; in clk_gfx3d_determine_rate()
1269 ret = __clk_determine_rate(req->best_parent_hw, &parent_req); in clk_gfx3d_determine_rate()
1273 req->rate = req->best_parent_rate = parent_req.rate; in clk_gfx3d_determine_rate()
1274 req->rate /= mux_div; in clk_gfx3d_determine_rate()
1283 struct clk_rcg2 *rcg = &cgfx->rcg; in clk_gfx3d_set_rate_and_parent()
1287 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_gfx3d_set_rate_and_parent()
1289 if (cgfx->div > 1) in clk_gfx3d_set_rate_and_parent()
1290 cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT; in clk_gfx3d_set_rate_and_parent()
1292 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); in clk_gfx3d_set_rate_and_parent()
1327 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_set_force_enable()
1333 for (count = 500; count > 0; count--) { in clk_rcg2_set_force_enable()
1341 return -ETIMEDOUT; in clk_rcg2_set_force_enable()
1348 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_clear_force_enable()
1378 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in __clk_rcg2_shared_set_rate()
1381 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_rcg2_shared_set_rate()
1384 return -EINVAL; in __clk_rcg2_shared_set_rate()
1388 * In case clock is disabled, update the M, N and D registers, cache in __clk_rcg2_shared_set_rate()
1393 return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg); in __clk_rcg2_shared_set_rate()
1436 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg); in clk_rcg2_shared_enable()
1455 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_disable()
1458 * Park the RCG at a safe configuration - sourced off of safe source. in clk_rcg2_shared_disable()
1467 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_rcg2_shared_disable()
1468 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); in clk_rcg2_shared_disable()
1481 return __clk_rcg2_get_parent(hw, rcg->parked_cfg); in clk_rcg2_shared_get_parent()
1492 rcg->parked_cfg &= ~CFG_SRC_SEL_MASK; in clk_rcg2_shared_set_parent()
1493 rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_rcg2_shared_set_parent()
1508 return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg); in clk_rcg2_shared_recalc_rate()
1518 * 1. Sets rcg->parked_cfg to reflect the value at probe so that the in clk_rcg2_shared_init()
1577 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_no_init_park()
1609 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); in clk_rcg2_dfs_populate_freq()
1611 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_populate_freq()
1612 f->pre_div = 1; in clk_rcg2_dfs_populate_freq()
1614 f->pre_div = cfg & mask; in clk_rcg2_dfs_populate_freq()
1621 if (src == rcg->parent_map[i].cfg) { in clk_rcg2_dfs_populate_freq()
1622 f->src = rcg->parent_map[i].src; in clk_rcg2_dfs_populate_freq()
1623 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); in clk_rcg2_dfs_populate_freq()
1631 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_populate_freq()
1632 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), in clk_rcg2_dfs_populate_freq()
1635 f->m = val; in clk_rcg2_dfs_populate_freq()
1637 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), in clk_rcg2_dfs_populate_freq()
1641 val += f->m; in clk_rcg2_dfs_populate_freq()
1642 f->n = val; in clk_rcg2_dfs_populate_freq()
1645 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div); in clk_rcg2_dfs_populate_freq()
1656 return -ENOMEM; in clk_rcg2_dfs_populate_freq_table()
1657 rcg->freq_tbl = freq_tbl; in clk_rcg2_dfs_populate_freq_table()
1660 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); in clk_rcg2_dfs_populate_freq_table()
1671 if (!rcg->freq_tbl) { in clk_rcg2_dfs_determine_rate()
1687 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; in clk_rcg2_dfs_recalc_rate() local
1689 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1690 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); in clk_rcg2_dfs_recalc_rate()
1694 if (rcg->freq_tbl) in clk_rcg2_dfs_recalc_rate()
1695 return rcg->freq_tbl[level].freq; in clk_rcg2_dfs_recalc_rate()
1704 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), in clk_rcg2_dfs_recalc_rate()
1707 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_recalc_rate()
1715 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_recalc_rate()
1716 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1717 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); in clk_rcg2_dfs_recalc_rate()
1718 m &= mask; in clk_rcg2_dfs_recalc_rate()
1720 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1721 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); in clk_rcg2_dfs_recalc_rate()
1724 n += m; in clk_rcg2_dfs_recalc_rate()
1727 return calc_rate(parent_rate, m, n, mode, pre_div); in clk_rcg2_dfs_recalc_rate()
1740 struct clk_rcg2 *rcg = data->rcg; in clk_rcg2_enable_dfs()
1741 struct clk_init_data *init = data->init; in clk_rcg2_enable_dfs()
1745 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); in clk_rcg2_enable_dfs()
1747 return -EINVAL; in clk_rcg2_enable_dfs()
1756 init->flags |= CLK_GET_RATE_NOCACHE; in clk_rcg2_enable_dfs()
1757 init->ops = &clk_rcg2_dfs_ops; in clk_rcg2_enable_dfs()
1759 rcg->freq_tbl = NULL; in clk_rcg2_enable_dfs()
1784 u32 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dp_set_rate()
1787 unsigned long num, den; in clk_rcg2_dp_set_rate() local
1790 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_set_rate()
1791 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_set_rate()
1793 if (!num || !den) in clk_rcg2_dp_set_rate()
1794 return -EINVAL; in clk_rcg2_dp_set_rate()
1796 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_dp_set_rate()
1802 if (cfg == rcg->parent_map[i].cfg) { in clk_rcg2_dp_set_rate()
1803 f.src = rcg->parent_map[i].src; in clk_rcg2_dp_set_rate()
1812 if (num != den) { in clk_rcg2_dp_set_rate()
1813 f.m = num; in clk_rcg2_dp_set_rate()
1816 f.m = 0; in clk_rcg2_dp_set_rate()
1833 unsigned long num, den; in clk_rcg2_dp_determine_rate() local
1837 rational_best_approximation(req->best_parent_rate, req->rate, in clk_rcg2_dp_determine_rate()
1838 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_determine_rate()
1839 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_determine_rate()
1841 if (!num || !den) in clk_rcg2_dp_determine_rate()
1842 return -EINVAL; in clk_rcg2_dp_determine_rate()
1844 tmp = req->best_parent_rate * num; in clk_rcg2_dp_determine_rate()
1846 req->rate = tmp; in clk_rcg2_dp_determine_rate()