18 static u32 ns_to_src(struct src_sel *s, u32 ns)  in ns_to_src()  argument
20 	ns >>= s->src_sel_shift;  in ns_to_src()
21 	ns &= SRC_SEL_MASK;  in ns_to_src()
22 	return ns;  in ns_to_src()
25 static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)  in src_to_ns()  argument
31 	ns &= ~mask;  in src_to_ns()
33 	ns |= src << s->src_sel_shift;  in src_to_ns()
34 	return ns;  in src_to_ns()
41 	u32 ns;  in clk_rcg_get_parent()  local
44 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_get_parent()
47 	ns = ns_to_src(&rcg->s, ns);  in clk_rcg_get_parent()
49 		if (ns == rcg->s.parent_map[i].cfg)  in clk_rcg_get_parent()
68 	u32 ns, reg;  in clk_dyn_rcg_get_parent()  local
79 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_get_parent()
82 	ns = ns_to_src(s, ns);  in clk_dyn_rcg_get_parent()
85 		if (ns == s->parent_map[i].cfg)  in clk_dyn_rcg_get_parent()
97 	u32 ns;  in clk_rcg_set_parent()  local
99 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_set_parent()
100 	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);  in clk_rcg_set_parent()
101 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in clk_rcg_set_parent()
113 static u32 ns_to_pre_div(struct pre_div *p, u32 ns)  in ns_to_pre_div()  argument
115 	ns >>= p->pre_div_shift;  in ns_to_pre_div()
116 	ns &= BIT(p->pre_div_width) - 1;  in ns_to_pre_div()
117 	return ns;  in ns_to_pre_div()
120 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)  in pre_div_to_ns()  argument
126 	ns &= ~mask;  in pre_div_to_ns()
128 	ns |= pre_div << p->pre_div_shift;  in pre_div_to_ns()
129 	return ns;  in pre_div_to_ns()
149 static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)  in ns_m_to_n()  argument
151 	ns = ~ns >> mn->n_val_shift;  in ns_m_to_n()
152 	ns &= BIT(mn->width) - 1;  in ns_m_to_n()
153 	return ns + m;  in ns_m_to_n()
163 static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)  in mn_to_ns()  argument
169 	ns &= ~mask;  in mn_to_ns()
176 		ns |= n;  in mn_to_ns()
179 	return ns;  in mn_to_ns()
200 	u32 ns, md, reg;  in configure_bank()  local
220 	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);  in configure_bank()
228 		ns |= BIT(mn->mnctr_reset_bit);  in configure_bank()
229 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
240 		ns = mn_to_ns(mn, f->m, f->n, ns);  in configure_bank()
241 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
245 		/* Two NS registers means mode control is in NS register */  in configure_bank()
247 			ns = mn_to_reg(mn, f->m, f->n, ns);  in configure_bank()
248 			ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
259 		ns &= ~BIT(mn->mnctr_reset_bit);  in configure_bank()
260 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
267 		ns = pre_div_to_ns(p, f->pre_div - 1, ns);  in configure_bank()
274 	ns = src_to_ns(s, s->parent_map[index].cfg, ns);  in configure_bank()
275 	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
294 	u32 ns, md, reg;  in clk_dyn_rcg_set_parent()  local
303 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_set_parent()
308 		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);  in clk_dyn_rcg_set_parent()
312 		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;  in clk_dyn_rcg_set_parent()
345 	u32 pre_div, m = 0, n = 0, ns, md, mode = 0;  in clk_rcg_recalc_rate()  local
348 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_recalc_rate()
349 	pre_div = ns_to_pre_div(&rcg->p, ns);  in clk_rcg_recalc_rate()
354 		n = ns_m_to_n(mn, ns, m);  in clk_rcg_recalc_rate()
359 			mode = ns;  in clk_rcg_recalc_rate()
370 	u32 m, n, pre_div, ns, md, mode, reg;  in clk_dyn_rcg_recalc_rate()  local
379 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_recalc_rate()
386 		n = ns_m_to_n(mn, ns, m);  in clk_dyn_rcg_recalc_rate()
387 		/* Two NS registers means mode control is in NS register */  in clk_dyn_rcg_recalc_rate()
389 			reg = ns;  in clk_dyn_rcg_recalc_rate()
394 		pre_div = ns_to_pre_div(&rcg->p[bank], ns);  in clk_dyn_rcg_recalc_rate()
476 	u32 ns, md, ctl;  in __clk_rcg_set_rate()  local
494 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
501 			ns = mn_to_reg(mn, f->m, f->n, ns);  in __clk_rcg_set_rate()
503 		ns = mn_to_ns(mn, f->m, f->n, ns);  in __clk_rcg_set_rate()
505 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
508 	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);  in __clk_rcg_set_rate()
509 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in __clk_rcg_set_rate()
567 	u32 ns, src;  in clk_rcg_bypass2_set_rate()  local
570 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_bypass2_set_rate()
574 	src = ns_to_src(&rcg->s, ns);  in clk_rcg_bypass2_set_rate()
575 	f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;  in clk_rcg_bypass2_set_rate()
638 	u32 ns, src;  in clk_rcg_pixel_set_rate()  local
641 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_pixel_set_rate()
645 	src = ns_to_src(&rcg->s, ns);  in clk_rcg_pixel_set_rate()
711 	u32 ns;  in clk_rcg_esc_set_rate()  local
717 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_esc_set_rate()
721 	ns = ns_to_src(&rcg->s, ns);  in clk_rcg_esc_set_rate()
724 		if (ns == rcg->s.parent_map[i].cfg) {  in clk_rcg_esc_set_rate()