1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_enable()
35 	/* Skip if already enabled or in FSM mode */  in clk_pll_enable()
40 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_enable()
47 	 * de-asserting the reset. Delay 10us just to be safe.  in clk_pll_enable()
51 	/* De-assert active-low PLL reset. */  in clk_pll_enable()
52 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_enable()
61 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_enable()
71 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_disable()
72 	/* Skip if in FSM mode */  in clk_pll_disable()
76 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);  in clk_pll_disable()
83 	u32 l, m, n, config;  in clk_pll_recalc_rate()  local
87 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);  in clk_pll_recalc_rate()
88 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);  in clk_pll_recalc_rate()
89 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);  in clk_pll_recalc_rate()
102 	if (pll->post_div_width) {  in clk_pll_recalc_rate()
103 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
104 		config >>= pll->post_div_shift;  in clk_pll_recalc_rate()
105 		config &= BIT(pll->post_div_width) - 1;  in clk_pll_recalc_rate()
106 		rate /= config + 1;  in clk_pll_recalc_rate()
118 	for (; f->freq; f++)  in find_freq()
119 		if (rate <= f->freq)  in find_freq()
131 	f = find_freq(pll->freq_tbl, req->rate);  in clk_pll_determine_rate()
133 		req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);  in clk_pll_determine_rate()
135 		req->rate = f->freq;  in clk_pll_determine_rate()
149 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_set_rate()
151 		return -EINVAL;  in clk_pll_set_rate()
153 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_set_rate()
159 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_set_rate()
160 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_set_rate()
161 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_set_rate()
162 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);  in clk_pll_set_rate()
184 	const char *name = clk_hw_get_name(&pll->clkr.hw);  in wait_for_pll()
187 	for (count = 200; count > 0; count--) {  in wait_for_pll()
188 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);  in wait_for_pll()
191 		if (val & BIT(pll->status_bit))  in wait_for_pll()
197 	return -ETIMEDOUT;  in wait_for_pll()
219 	const struct pll_config *config)  in clk_pll_configure()  argument
224 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
225 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
226 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
228 	val = config->vco_val;  in clk_pll_configure()
229 	val |= config->pre_div_val;  in clk_pll_configure()
230 	val |= config->post_div_val;  in clk_pll_configure()
231 	val |= config->mn_ena_mask;  in clk_pll_configure()
232 	val |= config->main_output_mask;  in clk_pll_configure()
233 	val |= config->aux_output_mask;  in clk_pll_configure()
235 	mask = config->vco_mask;  in clk_pll_configure()
236 	mask |= config->pre_div_mask;  in clk_pll_configure()
237 	mask |= config->post_div_mask;  in clk_pll_configure()
238 	mask |= config->mn_ena_mask;  in clk_pll_configure()
239 	mask |= config->main_output_mask;  in clk_pll_configure()
240 	mask |= config->aux_output_mask;  in clk_pll_configure()
242 	regmap_update_bits(regmap, pll->config_reg, mask, val);  in clk_pll_configure()
246 		const struct pll_config *config, bool fsm_mode)  in clk_pll_configure_sr()  argument
248 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr()
250 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);  in clk_pll_configure_sr()
255 		const struct pll_config *config, bool fsm_mode)  in clk_pll_configure_sr_hpm_lp()  argument
257 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr_hpm_lp()
259 		qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);  in clk_pll_configure_sr_hpm_lp()
269 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_enable()
274 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_sr2_enable()
281 	 * de-asserting the reset. Delay 10us just to be safe.  in clk_pll_sr2_enable()
285 	/* De-assert active-low PLL reset. */  in clk_pll_sr2_enable()
286 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_sr2_enable()
296 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_sr2_enable()
309 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_sr2_set_rate()
311 		return -EINVAL;  in clk_pll_sr2_set_rate()
313 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_sr2_set_rate()
319 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_sr2_set_rate()
320 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_sr2_set_rate()
321 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_sr2_set_rate()