Lines Matching +full:vco +full:- +full:offset

1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
74 #define VCO(a, b, c) { \
81  * struct clk_alpha_pll - phase locked loop (PLL)
82  * @offset: base address of registers
84  * @vco_table: array of VCO settings
85  * @num_vco: number of VCO settings in @vco_table
90 	u32 offset;
105  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
106  * @offset: base address of registers
108  * @width: width of post-divider
109  * @post_div_shift: shift to differentiate between odd & even post-divider
110  * @post_div_table: table with PLL odd and even post-divider settings
111  * @num_post_div: Number of PLL post-divider settings
116 	u32 offset;