Lines Matching +full:pll +full:- +full:reset +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3])
62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
66 #define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) argument
340 /* TRION PLL specific settings and offsets */
344 /* LUCID PLL specific settings and offsets */
347 /* LUCID 5LPE PLL specific settings and offsets */
353 /* LUCID EVO PLL specific settings and offsets */
360 /* PONGO ELU PLL specific setting and offsets */
366 /* ZONDA PLL specific */
372 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
375 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
383 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
389 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
391 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
396 for (count = 1500; count > 0; count--) { in wait_for_pll()
397 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
409 return -ETIMEDOUT; in wait_for_pll()
412 #define wait_for_pll_enable_active(pll) \ argument
413 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
415 #define wait_for_pll_enable_lock(pll) \ argument
416 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
418 #define wait_for_zonda_pll_freq_lock(pll) \ argument
419 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
421 #define wait_for_pll_disable(pll) \ argument
422 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
424 #define wait_for_pll_offline(pll) \ argument
425 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
427 #define wait_for_pll_update(pll) \ argument
428 wait_for_pll(pll, PLL_UPDATE, 1, "update")
430 #define wait_for_pll_update_ack_set(pll) \ argument
431 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
433 #define wait_for_pll_update_ack_clear(pll) \ argument
434 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
443 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_alpha_pll_configure() argument
448 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
449 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
450 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
452 if (pll_has_64bit_config(pll)) in clk_alpha_pll_configure()
453 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_alpha_pll_configure()
454 config->config_ctl_hi_val); in clk_alpha_pll_configure()
456 if (pll_alpha_width(pll) > 32) in clk_alpha_pll_configure()
457 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
459 val = config->main_output_mask; in clk_alpha_pll_configure()
460 val |= config->aux_output_mask; in clk_alpha_pll_configure()
461 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
462 val |= config->early_output_mask; in clk_alpha_pll_configure()
463 val |= config->pre_div_val; in clk_alpha_pll_configure()
464 val |= config->post_div_val; in clk_alpha_pll_configure()
465 val |= config->vco_val; in clk_alpha_pll_configure()
466 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
467 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
469 mask = config->main_output_mask; in clk_alpha_pll_configure()
470 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
471 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
472 mask |= config->early_output_mask; in clk_alpha_pll_configure()
473 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
474 mask |= config->post_div_mask; in clk_alpha_pll_configure()
475 mask |= config->vco_mask; in clk_alpha_pll_configure()
476 mask |= config->alpha_en_mask; in clk_alpha_pll_configure()
477 mask |= config->alpha_mode_mask; in clk_alpha_pll_configure()
479 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_alpha_pll_configure()
481 if (config->test_ctl_mask) in clk_alpha_pll_configure()
482 regmap_update_bits(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
483 config->test_ctl_mask, in clk_alpha_pll_configure()
484 config->test_ctl_val); in clk_alpha_pll_configure()
486 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_alpha_pll_configure()
487 config->test_ctl_val); in clk_alpha_pll_configure()
489 if (config->test_ctl_hi_mask) in clk_alpha_pll_configure()
490 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
491 config->test_ctl_hi_mask, in clk_alpha_pll_configure()
492 config->test_ctl_hi_val); in clk_alpha_pll_configure()
494 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_alpha_pll_configure()
495 config->test_ctl_hi_val); in clk_alpha_pll_configure()
497 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
498 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_alpha_pll_configure()
505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_enable() local
508 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
514 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
517 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
524 return wait_for_pll_enable_active(pll); in clk_alpha_pll_hwfsm_enable()
530 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_hwfsm_disable() local
533 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
537 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
538 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
543 ret = wait_for_pll_offline(pll); in clk_alpha_pll_hwfsm_disable()
549 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
554 wait_for_pll_disable(pll); in clk_alpha_pll_hwfsm_disable()
560 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in pll_is_enabled() local
563 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
583 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_enable() local
587 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
591 /* If in FSM mode, just vote for it */ in clk_alpha_pll_enable()
596 return wait_for_pll_enable_active(pll); in clk_alpha_pll_enable()
603 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
610 * de-asserting the reset. in clk_alpha_pll_enable()
615 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
620 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_enable()
624 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
635 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_disable() local
638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
642 /* If in FSM mode, just unvote it */ in clk_alpha_pll_disable()
649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
656 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
694 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) in alpha_pll_find_vco() argument
696 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
697 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
700 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
711 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_recalc_rate() local
712 u32 alpha_width = pll_alpha_width(pll); in clk_alpha_pll_recalc_rate()
714 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_alpha_pll_recalc_rate()
717 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in clk_alpha_pll_recalc_rate()
721 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low)) in clk_alpha_pll_recalc_rate()
724 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
729 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
733 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
740 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) in __clk_alpha_pll_update_latch() argument
743 u32 mode; in __clk_alpha_pll_update_latch() local
745 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
747 /* Latch the input to the PLL */ in __clk_alpha_pll_update_latch()
748 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
755 * PLL will latch the new L, Alpha and freq control word. in __clk_alpha_pll_update_latch()
756 * PLL will respond by raising PLL_ACK_LATCH output when new programming in __clk_alpha_pll_update_latch()
757 * has been latched in and PLL is being updated. When in __clk_alpha_pll_update_latch()
759 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. in __clk_alpha_pll_update_latch()
761 if (mode & PLL_UPDATE_BYPASS) { in __clk_alpha_pll_update_latch()
762 ret = wait_for_pll_update_ack_set(pll); in __clk_alpha_pll_update_latch()
766 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
768 ret = wait_for_pll_update(pll); in __clk_alpha_pll_update_latch()
773 ret = wait_for_pll_update_ack_clear(pll); in __clk_alpha_pll_update_latch()
777 /* Wait for PLL output to stabilize */ in __clk_alpha_pll_update_latch()
783 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, in clk_alpha_pll_update_latch() argument
786 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
787 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
790 return __clk_alpha_pll_update_latch(pll); in clk_alpha_pll_update_latch()
793 static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco, in clk_alpha_pll_update_configs() argument
796 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_update_configs()
799 alpha <<= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_update_configs()
802 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha)); in clk_alpha_pll_update_configs()
804 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha)); in clk_alpha_pll_update_configs()
807 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_update_configs()
809 vco->val << PLL_VCO_SHIFT); in clk_alpha_pll_update_configs()
813 regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); in clk_alpha_pll_update_configs()
820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __clk_alpha_pll_set_rate() local
822 u32 l, alpha_width = pll_alpha_width(pll); in __clk_alpha_pll_set_rate()
826 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
827 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
828 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
830 return -EINVAL; in __clk_alpha_pll_set_rate()
833 clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true); in __clk_alpha_pll_set_rate()
835 return clk_alpha_pll_update_latch(pll, is_enabled); in __clk_alpha_pll_set_rate()
855 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_determine_rate() local
856 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_determine_rate()
860 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, in clk_alpha_pll_determine_rate()
862 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) in clk_alpha_pll_determine_rate()
865 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_determine_rate()
866 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_determine_rate()
868 req->rate = clamp(req->rate, min_freq, max_freq); in clk_alpha_pll_determine_rate()
873 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_huayra_2290_pll_configure() argument
878 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_huayra_2290_pll_configure()
879 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_huayra_2290_pll_configure()
880 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_huayra_2290_pll_configure()
881 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_huayra_2290_pll_configure()
882 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_huayra_2290_pll_configure()
883 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_huayra_2290_pll_configure()
884 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_huayra_2290_pll_configure()
885 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_huayra_2290_pll_configure()
886 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_huayra_2290_pll_configure()
889 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_huayra_2290_pll_configure()
890 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
892 /* Wait 5 us between setting BYPASS and deasserting reset */ in clk_huayra_2290_pll_configure()
895 /* Take PLL out from reset state */ in clk_huayra_2290_pll_configure()
896 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_huayra_2290_pll_configure()
897 regmap_read(regmap, PLL_MODE(pll), &val); in clk_huayra_2290_pll_configure()
902 /* Enable PLL output */ in clk_huayra_2290_pll_configure()
903 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_huayra_2290_pll_configure()
912 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
914 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
915 l -= 1; in alpha_huayra_pll_calc_rate()
944 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
947 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
958 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_recalc_rate() local
961 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in alpha_pll_huayra_recalc_rate()
964 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in alpha_pll_huayra_recalc_rate()
968 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
976 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
977 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
980 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
994 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
995 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
998 rate -= tmp; in alpha_pll_huayra_recalc_rate()
1014 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_huayra_set_rate() local
1019 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
1022 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
1025 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, in alpha_pll_huayra_set_rate()
1032 return -EBUSY; in alpha_pll_huayra_set_rate()
1035 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1038 return wait_for_pll_enable_lock(pll); in alpha_pll_huayra_set_rate()
1041 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
1042 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
1045 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1048 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
1059 req->rate = alpha_huayra_pll_round_rate(req->rate, in alpha_pll_huayra_determine_rate()
1060 req->best_parent_rate, &l, &a); in alpha_pll_huayra_determine_rate()
1065 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, in trion_pll_is_enabled() argument
1071 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); in trion_pll_is_enabled()
1072 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in trion_pll_is_enabled()
1081 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_is_enabled() local
1083 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
1088 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_enable() local
1089 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
1093 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_enable()
1097 /* If in FSM mode, just vote for it */ in clk_trion_pll_enable()
1102 return wait_for_pll_enable_active(pll); in clk_trion_pll_enable()
1105 /* Set operation mode to RUN */ in clk_trion_pll_enable()
1106 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_trion_pll_enable()
1108 ret = wait_for_pll_enable_lock(pll); in clk_trion_pll_enable()
1112 /* Enable the PLL outputs */ in clk_trion_pll_enable()
1113 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_enable()
1118 /* Enable the global PLL outputs */ in clk_trion_pll_enable()
1119 return regmap_update_bits(regmap, PLL_MODE(pll), in clk_trion_pll_enable()
1125 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_disable() local
1126 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
1130 ret = regmap_read(regmap, PLL_MODE(pll), &val); in clk_trion_pll_disable()
1134 /* If in FSM mode, just unvote it */ in clk_trion_pll_disable()
1140 /* Disable the global PLL output */ in clk_trion_pll_disable()
1141 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1145 /* Disable the PLL outputs */ in clk_trion_pll_disable()
1146 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_disable()
1151 /* Place the PLL mode in STANDBY */ in clk_trion_pll_disable()
1152 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_disable()
1153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1159 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_trion_pll_recalc_rate() local
1160 u32 l, frac, alpha_width = pll_alpha_width(pll); in clk_trion_pll_recalc_rate()
1162 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_trion_pll_recalc_rate()
1165 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) in clk_trion_pll_recalc_rate()
1221 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_recalc_rate() local
1224 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) in clk_alpha_pll_postdiv_recalc_rate()
1228 ctl &= PLL_POST_DIV_MASK(pll); in clk_alpha_pll_postdiv_recalc_rate()
1252 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_determine_rate() local
1255 if (pll->width == 2) in clk_alpha_pll_postdiv_determine_rate()
1260 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, in clk_alpha_pll_postdiv_determine_rate()
1261 table, pll->width, in clk_alpha_pll_postdiv_determine_rate()
1270 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_ro_determine_rate() local
1273 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_ro_determine_rate()
1276 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_ro_determine_rate()
1280 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), in clk_alpha_pll_postdiv_ro_determine_rate()
1281 div * req->rate); in clk_alpha_pll_postdiv_ro_determine_rate()
1283 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); in clk_alpha_pll_postdiv_ro_determine_rate()
1291 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_set_rate() local
1294 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
1295 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
1297 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1298 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, in clk_alpha_pll_postdiv_set_rate()
1315 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_fabia_pll_configure() argument
1320 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1321 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1322 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_fabia_pll_configure()
1323 config->config_ctl_val); in clk_fabia_pll_configure()
1324 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_fabia_pll_configure()
1325 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1326 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_fabia_pll_configure()
1327 config->user_ctl_val); in clk_fabia_pll_configure()
1328 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_fabia_pll_configure()
1329 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1330 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_fabia_pll_configure()
1331 config->test_ctl_val); in clk_fabia_pll_configure()
1332 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_fabia_pll_configure()
1333 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1335 if (config->post_div_mask) { in clk_fabia_pll_configure()
1336 mask = config->post_div_mask; in clk_fabia_pll_configure()
1337 val = config->post_div_val; in clk_fabia_pll_configure()
1338 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_fabia_pll_configure()
1341 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) in clk_fabia_pll_configure()
1342 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, in clk_fabia_pll_configure()
1345 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_fabia_pll_configure()
1348 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1355 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_enable() local
1357 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1359 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_enable()
1363 /* If in FSM mode, just vote for it */ in alpha_pll_fabia_enable()
1368 return wait_for_pll_enable_active(pll); in alpha_pll_fabia_enable()
1371 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); in alpha_pll_fabia_enable()
1375 /* Skip If PLL is already running */ in alpha_pll_fabia_enable()
1379 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1383 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_enable()
1387 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1392 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_fabia_enable()
1396 ret = wait_for_pll_enable_lock(pll); in alpha_pll_fabia_enable()
1400 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), in alpha_pll_fabia_enable()
1405 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
1412 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_disable() local
1414 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1416 ret = regmap_read(regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_disable()
1420 /* If in FSM mode, just unvote it */ in alpha_pll_fabia_disable()
1426 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_disable()
1431 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_fabia_disable()
1435 /* Place the PLL in STANDBY */ in alpha_pll_fabia_disable()
1436 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_fabia_disable()
1442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_recalc_rate() local
1443 u32 l, frac, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_recalc_rate()
1445 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in alpha_pll_fabia_recalc_rate()
1448 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) in alpha_pll_fabia_recalc_rate()
1466 return -EINVAL; in alpha_pll_check_rate_margin()
1475 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_set_rate() local
1476 u32 l, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_set_rate()
1487 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1488 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1490 return __clk_alpha_pll_update_latch(pll); in alpha_pll_fabia_set_rate()
1495 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_fabia_prepare() local
1499 u32 cal_l, val, alpha_width = pll_alpha_width(pll); in alpha_pll_fabia_prepare()
1504 /* Check if calibration needs to be done i.e. PLL is in reset */ in alpha_pll_fabia_prepare()
1505 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1513 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1515 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1516 return -EINVAL; in alpha_pll_fabia_prepare()
1519 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1520 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1524 return -EINVAL; in alpha_pll_fabia_prepare()
1533 /* Setup PLL for calibration frequency */ in alpha_pll_fabia_prepare()
1534 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1536 /* Bringup the PLL at calibration frequency */ in alpha_pll_fabia_prepare()
1539 pr_err("%s: alpha pll calibration failed\n", name); in alpha_pll_fabia_prepare()
1571 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_recalc_rate() local
1575 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1579 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1580 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1582 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1583 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1584 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1595 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_recalc_rate() local
1596 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1599 if (regmap_read(regmap, PLL_USER_CTL(pll), &val)) in clk_trion_pll_postdiv_recalc_rate()
1602 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1603 val &= PLL_POST_DIV_MASK(pll); in clk_trion_pll_postdiv_recalc_rate()
1605 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1606 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1607 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1618 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_determine_rate() local
1620 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, in clk_trion_pll_postdiv_determine_rate()
1621 pll->post_div_table, in clk_trion_pll_postdiv_determine_rate()
1622 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_determine_rate()
1631 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_trion_pll_postdiv_set_rate() local
1632 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1636 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1637 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1638 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1643 return regmap_update_bits(regmap, PLL_USER_CTL(pll), in clk_trion_pll_postdiv_set_rate()
1644 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, in clk_trion_pll_postdiv_set_rate()
1645 val << pll->post_div_shift); in clk_trion_pll_postdiv_set_rate()
1658 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_determine_rate() local
1660 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, in clk_alpha_pll_postdiv_fabia_determine_rate()
1661 pll->post_div_table, in clk_alpha_pll_postdiv_fabia_determine_rate()
1662 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_determine_rate()
1670 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in clk_alpha_pll_postdiv_fabia_set_rate() local
1674 * If the PLL is in FSM mode, then treat set_rate callback as a in clk_alpha_pll_postdiv_fabia_set_rate()
1675 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1677 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1685 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1686 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1687 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1692 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1693 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1694 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1705 * clk_trion_pll_configure - configure the trion pll
1707 * @pll: clk alpha pll
1709 * @config: configuration to apply for pll
1711 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_trion_pll_configure() argument
1715 * If the bootloader left the PLL enabled it's likely that there are in clk_trion_pll_configure()
1716 * RCGs that will lock up if we disable the PLL below. in clk_trion_pll_configure()
1718 if (trion_pll_is_enabled(pll, regmap)) { in clk_trion_pll_configure()
1719 pr_debug("Trion PLL is already enabled, skipping configuration\n"); in clk_trion_pll_configure()
1723 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1724 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_trion_pll_configure()
1725 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1726 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_trion_pll_configure()
1727 config->config_ctl_val); in clk_trion_pll_configure()
1728 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_trion_pll_configure()
1729 config->config_ctl_hi_val); in clk_trion_pll_configure()
1730 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_trion_pll_configure()
1731 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1732 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_trion_pll_configure()
1733 config->user_ctl_val); in clk_trion_pll_configure()
1734 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_trion_pll_configure()
1735 config->user_ctl_hi_val); in clk_trion_pll_configure()
1736 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_trion_pll_configure()
1737 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1738 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_trion_pll_configure()
1739 config->test_ctl_val); in clk_trion_pll_configure()
1740 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_trion_pll_configure()
1741 config->test_ctl_hi_val); in clk_trion_pll_configure()
1742 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_trion_pll_configure()
1743 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1745 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, in clk_trion_pll_configure()
1748 /* Disable PLL output */ in clk_trion_pll_configure()
1749 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_configure()
1751 /* Set operation mode to OFF */ in clk_trion_pll_configure()
1752 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_trion_pll_configure()
1754 /* Place the PLL in STANDBY mode */ in clk_trion_pll_configure()
1755 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
1760 * The TRION PLL requires a power-on self-calibration which happens when the
1761 * PLL comes out of reset. Calibrate in case it is not completed.
1765 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_prepare() local
1770 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); in __alpha_pll_trion_prepare()
1795 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in __alpha_pll_trion_set_rate() local
1797 u32 val, l, alpha_width = pll_alpha_width(pll); in __alpha_pll_trion_set_rate()
1807 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); in __alpha_pll_trion_set_rate()
1808 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __alpha_pll_trion_set_rate()
1810 /* Latch the PLL input */ in __alpha_pll_trion_set_rate()
1811 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); in __alpha_pll_trion_set_rate()
1817 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in __alpha_pll_trion_set_rate()
1819 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); in __alpha_pll_trion_set_rate()
1820 return -EINVAL; in __alpha_pll_trion_set_rate()
1824 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); in __alpha_pll_trion_set_rate()
1829 ret = wait_for_pll_enable_lock(pll); in __alpha_pll_trion_set_rate()
1834 /* Wait for PLL output to stabilize */ in __alpha_pll_trion_set_rate()
1874 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_agera_pll_configure() argument
1877 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_agera_pll_configure()
1878 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_agera_pll_configure()
1879 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_agera_pll_configure()
1880 config->user_ctl_val); in clk_agera_pll_configure()
1881 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_agera_pll_configure()
1882 config->config_ctl_val); in clk_agera_pll_configure()
1883 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_agera_pll_configure()
1884 config->config_ctl_hi_val); in clk_agera_pll_configure()
1885 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_agera_pll_configure()
1886 config->test_ctl_val); in clk_agera_pll_configure()
1887 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_agera_pll_configure()
1888 config->test_ctl_hi_val); in clk_agera_pll_configure()
1895 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_agera_set_rate() local
1896 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_agera_set_rate()
1907 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_agera_set_rate()
1908 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_agera_set_rate()
1911 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_agera_set_rate()
1927 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1929 * @pll: clk alpha pll
1931 * @config: configuration to apply for pll
1933 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_5lpe_pll_configure() argument
1937 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_5lpe_pll_configure()
1938 * RCGs that will lock up if we disable the PLL below. in clk_lucid_5lpe_pll_configure()
1940 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_5lpe_pll_configure()
1941 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); in clk_lucid_5lpe_pll_configure()
1945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_lucid_5lpe_pll_configure()
1946 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); in clk_lucid_5lpe_pll_configure()
1947 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_5lpe_pll_configure()
1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), in clk_lucid_5lpe_pll_configure()
1949 config->config_ctl_val); in clk_lucid_5lpe_pll_configure()
1950 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1951 config->config_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1952 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1953 config->config_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1954 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_lucid_5lpe_pll_configure()
1955 config->user_ctl_val); in clk_lucid_5lpe_pll_configure()
1956 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1957 config->user_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1958 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1959 config->user_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1960 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), in clk_lucid_5lpe_pll_configure()
1961 config->test_ctl_val); in clk_lucid_5lpe_pll_configure()
1962 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), in clk_lucid_5lpe_pll_configure()
1963 config->test_ctl_hi_val); in clk_lucid_5lpe_pll_configure()
1964 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), in clk_lucid_5lpe_pll_configure()
1965 config->test_ctl_hi1_val); in clk_lucid_5lpe_pll_configure()
1967 /* Disable PLL output */ in clk_lucid_5lpe_pll_configure()
1968 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_5lpe_pll_configure()
1970 /* Set operation mode to OFF */ in clk_lucid_5lpe_pll_configure()
1971 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_5lpe_pll_configure()
1973 /* Place the PLL in STANDBY mode */ in clk_lucid_5lpe_pll_configure()
1974 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_5lpe_pll_configure()
1980 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_enable() local
1984 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_enable()
1988 /* If in FSM mode, just vote for it */ in alpha_pll_lucid_5lpe_enable()
1993 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
1996 /* Check if PLL is already enabled, return if enabled */ in alpha_pll_lucid_5lpe_enable()
1997 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) in alpha_pll_lucid_5lpe_enable()
2000 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_5lpe_enable()
2004 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_5lpe_enable()
2006 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_5lpe_enable()
2010 /* Enable the PLL outputs */ in alpha_pll_lucid_5lpe_enable()
2011 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_5lpe_enable()
2015 /* Enable the global PLL outputs */ in alpha_pll_lucid_5lpe_enable()
2016 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_5lpe_enable()
2021 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_disable() local
2025 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_5lpe_disable()
2029 /* If in FSM mode, just unvote it */ in alpha_pll_lucid_5lpe_disable()
2035 /* Disable the global PLL output */ in alpha_pll_lucid_5lpe_disable()
2036 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_lucid_5lpe_disable()
2040 /* Disable the PLL outputs */ in alpha_pll_lucid_5lpe_disable()
2041 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in alpha_pll_lucid_5lpe_disable()
2045 /* Place the PLL mode in STANDBY */ in alpha_pll_lucid_5lpe_disable()
2046 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_lucid_5lpe_disable()
2050 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
2051 * when the PLL comes out of reset. Calibrate in case it is not completed.
2055 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_5lpe_prepare() local
2061 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_lucid_5lpe_prepare()
2067 return -EINVAL; in alpha_pll_lucid_5lpe_prepare()
2090 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); in __clk_lucid_pll_postdiv_set_rate() local
2091 struct regmap *regmap = pll->clkr.regmap; in __clk_lucid_pll_postdiv_set_rate()
2096 * If the PLL is in FSM mode, then treat set_rate callback as a in __clk_lucid_pll_postdiv_set_rate()
2097 * no-operation. in __clk_lucid_pll_postdiv_set_rate()
2099 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in __clk_lucid_pll_postdiv_set_rate()
2106 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2107 pr_err("Missing the post_div_table for the %s PLL\n", in __clk_lucid_pll_postdiv_set_rate()
2108 clk_hw_get_name(&pll->clkr.hw)); in __clk_lucid_pll_postdiv_set_rate()
2109 return -EINVAL; in __clk_lucid_pll_postdiv_set_rate()
2113 for (i = 0; i < pll->num_post_div; i++) { in __clk_lucid_pll_postdiv_set_rate()
2114 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
2115 val = pll->post_div_table[i].val; in __clk_lucid_pll_postdiv_set_rate()
2120 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2121 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_lucid_pll_postdiv_set_rate()
2122 mask, val << pll->post_div_shift); in __clk_lucid_pll_postdiv_set_rate()
2158 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_zonda_pll_configure() argument
2161 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_zonda_pll_configure()
2162 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_zonda_pll_configure()
2163 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_zonda_pll_configure()
2164 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_zonda_pll_configure()
2165 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_zonda_pll_configure()
2166 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_zonda_pll_configure()
2167 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_zonda_pll_configure()
2168 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_zonda_pll_configure()
2169 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_zonda_pll_configure()
2170 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_zonda_pll_configure()
2171 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_zonda_pll_configure()
2173 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); in clk_zonda_pll_configure()
2175 /* Disable PLL output */ in clk_zonda_pll_configure()
2176 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_configure()
2178 /* Set operation mode to OFF */ in clk_zonda_pll_configure()
2179 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_zonda_pll_configure()
2181 /* Place the PLL in STANDBY mode */ in clk_zonda_pll_configure()
2182 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_configure()
2188 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_enable() local
2189 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_enable()
2193 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_enable()
2195 /* If in FSM mode, just vote for it */ in clk_zonda_pll_enable()
2200 return wait_for_pll_enable_active(pll); in clk_zonda_pll_enable()
2203 /* Get the PLL out of bypass mode */ in clk_zonda_pll_enable()
2204 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); in clk_zonda_pll_enable()
2208 * de-asserting the reset. in clk_zonda_pll_enable()
2212 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_zonda_pll_enable()
2214 /* Set operation mode to RUN */ in clk_zonda_pll_enable()
2215 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in clk_zonda_pll_enable()
2217 regmap_read(regmap, PLL_TEST_CTL(pll), &val); in clk_zonda_pll_enable()
2219 /* If cfa mode then poll for freq lock */ in clk_zonda_pll_enable()
2221 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_enable()
2223 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_enable()
2227 /* Enable the PLL outputs */ in clk_zonda_pll_enable()
2228 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); in clk_zonda_pll_enable()
2230 /* Enable the global PLL outputs */ in clk_zonda_pll_enable()
2231 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in clk_zonda_pll_enable()
2238 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_disable() local
2239 struct regmap *regmap = pll->clkr.regmap; in clk_zonda_pll_disable()
2242 regmap_read(regmap, PLL_MODE(pll), &val); in clk_zonda_pll_disable()
2244 /* If in FSM mode, just unvote it */ in clk_zonda_pll_disable()
2250 /* Disable the global PLL output */ in clk_zonda_pll_disable()
2251 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_zonda_pll_disable()
2253 /* Disable the PLL outputs */ in clk_zonda_pll_disable()
2254 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); in clk_zonda_pll_disable()
2256 /* Put the PLL in bypass and reset */ in clk_zonda_pll_disable()
2257 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); in clk_zonda_pll_disable()
2259 /* Place the PLL mode in OFF state */ in clk_zonda_pll_disable()
2260 regmap_write(regmap, PLL_OPMODE(pll), 0x0); in clk_zonda_pll_disable()
2276 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_zonda_pll_set_rate() local
2279 u32 l, alpha_width = pll_alpha_width(pll); in clk_zonda_pll_set_rate()
2292 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_zonda_pll_set_rate()
2293 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_zonda_pll_set_rate()
2301 /* Read stay in cfa mode */ in clk_zonda_pll_set_rate()
2302 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); in clk_zonda_pll_set_rate()
2304 /* If cfa mode then poll for freq lock */ in clk_zonda_pll_set_rate()
2306 ret = wait_for_zonda_pll_freq_lock(pll); in clk_zonda_pll_set_rate()
2308 ret = wait_for_pll_enable_lock(pll); in clk_zonda_pll_set_rate()
2312 /* Wait for PLL output to stabilize */ in clk_zonda_pll_set_rate()
2327 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_evo_pll_configure() argument
2330 u32 lval = config->l; in clk_lucid_evo_pll_configure()
2333 * If the bootloader left the PLL enabled it's likely that there are in clk_lucid_evo_pll_configure()
2334 * RCGs that will lock up if we disable the PLL below. in clk_lucid_evo_pll_configure()
2336 if (trion_pll_is_enabled(pll, regmap)) { in clk_lucid_evo_pll_configure()
2337 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); in clk_lucid_evo_pll_configure()
2342 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_evo_pll_configure()
2343 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_evo_pll_configure()
2344 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_evo_pll_configure()
2345 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_evo_pll_configure()
2346 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2347 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_evo_pll_configure()
2348 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_evo_pll_configure()
2349 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_evo_pll_configure()
2350 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_evo_pll_configure()
2351 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_evo_pll_configure()
2352 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_evo_pll_configure()
2354 /* Disable PLL output */ in clk_lucid_evo_pll_configure()
2355 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_evo_pll_configure()
2357 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_evo_pll_configure()
2358 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_evo_pll_configure()
2359 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_evo_pll_configure()
2363 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_lucid_ole_pll_configure() argument
2366 u32 lval = config->l; in clk_lucid_ole_pll_configure()
2370 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); in clk_lucid_ole_pll_configure()
2371 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_lucid_ole_pll_configure()
2372 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_lucid_ole_pll_configure()
2373 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_lucid_ole_pll_configure()
2374 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2375 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_lucid_ole_pll_configure()
2376 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_lucid_ole_pll_configure()
2377 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_lucid_ole_pll_configure()
2378 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_lucid_ole_pll_configure()
2379 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_lucid_ole_pll_configure()
2380 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_lucid_ole_pll_configure()
2382 /* Disable PLL output */ in clk_lucid_ole_pll_configure()
2383 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_lucid_ole_pll_configure()
2385 /* Set operation mode to STANDBY and de-assert the reset */ in clk_lucid_ole_pll_configure()
2386 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_lucid_ole_pll_configure()
2387 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_lucid_ole_pll_configure()
2393 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_enable() local
2394 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_enable()
2398 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in alpha_pll_lucid_evo_enable()
2402 /* If in FSM mode, just vote for it */ in alpha_pll_lucid_evo_enable()
2407 return wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2410 /* Check if PLL is already enabled */ in alpha_pll_lucid_evo_enable()
2411 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_lucid_evo_enable()
2414 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_lucid_evo_enable()
2418 /* Set operation mode to RUN */ in alpha_pll_lucid_evo_enable()
2419 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_lucid_evo_enable()
2421 ret = wait_for_pll_enable_lock(pll); in alpha_pll_lucid_evo_enable()
2425 /* Enable the PLL outputs */ in alpha_pll_lucid_evo_enable()
2426 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); in alpha_pll_lucid_evo_enable()
2430 /* Enable the global PLL outputs */ in alpha_pll_lucid_evo_enable()
2431 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_lucid_evo_enable()
2440 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) in _alpha_pll_lucid_evo_disable() argument
2442 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_disable() local
2443 struct regmap *regmap = pll->clkr.regmap; in _alpha_pll_lucid_evo_disable()
2447 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); in _alpha_pll_lucid_evo_disable()
2451 /* If in FSM mode, just unvote it */ in _alpha_pll_lucid_evo_disable()
2457 /* Disable the global PLL output */ in _alpha_pll_lucid_evo_disable()
2458 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in _alpha_pll_lucid_evo_disable()
2462 /* Disable the PLL outputs */ in _alpha_pll_lucid_evo_disable()
2463 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); in _alpha_pll_lucid_evo_disable()
2467 /* Place the PLL mode in STANDBY */ in _alpha_pll_lucid_evo_disable()
2468 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in _alpha_pll_lucid_evo_disable()
2470 if (reset) in _alpha_pll_lucid_evo_disable()
2471 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); in _alpha_pll_lucid_evo_disable()
2474 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) in _alpha_pll_lucid_evo_prepare() argument
2476 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in _alpha_pll_lucid_evo_prepare() local
2482 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in _alpha_pll_lucid_evo_prepare()
2488 return -EINVAL; in _alpha_pll_lucid_evo_prepare()
2494 _alpha_pll_lucid_evo_disable(hw, reset); in _alpha_pll_lucid_evo_prepare()
2522 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_lucid_evo_recalc_rate() local
2523 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_lucid_evo_recalc_rate()
2526 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) in alpha_pll_lucid_evo_recalc_rate()
2530 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) in alpha_pll_lucid_evo_recalc_rate()
2533 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); in alpha_pll_lucid_evo_recalc_rate()
2582 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_prepare() local
2583 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_prepare()
2586 /* Enable PLL intially to one-time calibrate against XO. */ in alpha_pll_pongo_elu_prepare()
2587 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_prepare()
2588 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_prepare()
2589 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); in alpha_pll_pongo_elu_prepare()
2592 pll->clkr.regmap = regmap; in alpha_pll_pongo_elu_prepare()
2593 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_prepare()
2595 /* Reverse calibration - disable PLL output */ in alpha_pll_pongo_elu_prepare()
2596 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_prepare()
2600 /* Disable PLL after one-time calibration. */ in alpha_pll_pongo_elu_prepare()
2601 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_prepare()
2604 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, in alpha_pll_pongo_elu_prepare()
2612 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_enable() local
2613 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_enable()
2616 /* Check if PLL is already enabled */ in alpha_pll_pongo_elu_enable()
2617 if (trion_pll_is_enabled(pll, regmap)) in alpha_pll_pongo_elu_enable()
2620 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in alpha_pll_pongo_elu_enable()
2624 /* Set operation mode to RUN */ in alpha_pll_pongo_elu_enable()
2625 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); in alpha_pll_pongo_elu_enable()
2627 ret = wait_for_pll_enable_lock(pll); in alpha_pll_pongo_elu_enable()
2631 /* Enable the global PLL outputs */ in alpha_pll_pongo_elu_enable()
2632 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); in alpha_pll_pongo_elu_enable()
2644 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_disable() local
2645 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_disable()
2648 /* Disable the global PLL output */ in alpha_pll_pongo_elu_disable()
2649 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_pongo_elu_disable()
2653 /* Place the PLL mode in STANDBY */ in alpha_pll_pongo_elu_disable()
2654 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in alpha_pll_pongo_elu_disable()
2660 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in alpha_pll_pongo_elu_recalc_rate() local
2661 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_pongo_elu_recalc_rate()
2664 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) in alpha_pll_pongo_elu_recalc_rate()
2669 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); in alpha_pll_pongo_elu_recalc_rate()
2680 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, in clk_pongo_elu_pll_configure() argument
2686 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, in clk_pongo_elu_pll_configure()
2689 if (trion_pll_is_enabled(pll, regmap)) in clk_pongo_elu_pll_configure()
2692 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) in clk_pongo_elu_pll_configure()
2698 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_pongo_elu_pll_configure()
2699 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_pongo_elu_pll_configure()
2700 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_pongo_elu_pll_configure()
2701 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_pongo_elu_pll_configure()
2702 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2703 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2704 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), in clk_pongo_elu_pll_configure()
2705 config->user_ctl_val | PONGO_PLL_OUT_MASK); in clk_pongo_elu_pll_configure()
2706 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_pongo_elu_pll_configure()
2707 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_pongo_elu_pll_configure()
2708 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_pongo_elu_pll_configure()
2709 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_pongo_elu_pll_configure()
2710 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); in clk_pongo_elu_pll_configure()
2711 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); in clk_pongo_elu_pll_configure()
2713 /* Disable PLL output */ in clk_pongo_elu_pll_configure()
2714 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_pongo_elu_pll_configure()
2718 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_rivian_evo_pll_configure() argument
2721 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_rivian_evo_pll_configure()
2722 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_rivian_evo_pll_configure()
2723 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_rivian_evo_pll_configure()
2724 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_rivian_evo_pll_configure()
2725 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_rivian_evo_pll_configure()
2726 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_rivian_evo_pll_configure()
2727 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_rivian_evo_pll_configure()
2728 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_rivian_evo_pll_configure()
2730 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_rivian_evo_pll_configure()
2732 regmap_update_bits(regmap, PLL_MODE(pll), in clk_rivian_evo_pll_configure()
2741 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_recalc_rate() local
2744 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) in clk_rivian_evo_pll_recalc_rate()
2753 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_rivian_evo_pll_determine_rate() local
2758 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, in clk_rivian_evo_pll_determine_rate()
2760 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) in clk_rivian_evo_pll_determine_rate()
2763 min_freq = pll->vco_table[0].min_freq; in clk_rivian_evo_pll_determine_rate()
2764 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_rivian_evo_pll_determine_rate()
2766 req->rate = clamp(req->rate, min_freq, max_freq); in clk_rivian_evo_pll_determine_rate()
2780 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_stromer_pll_configure() argument
2785 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_stromer_pll_configure()
2786 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_stromer_pll_configure()
2787 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_stromer_pll_configure()
2789 if (pll_has_64bit_config(pll)) in clk_stromer_pll_configure()
2790 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), in clk_stromer_pll_configure()
2791 config->config_ctl_hi_val); in clk_stromer_pll_configure()
2793 if (pll_alpha_width(pll) > 32) in clk_stromer_pll_configure()
2794 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_stromer_pll_configure()
2796 val = config->main_output_mask; in clk_stromer_pll_configure()
2797 val |= config->aux_output_mask; in clk_stromer_pll_configure()
2798 val |= config->aux2_output_mask; in clk_stromer_pll_configure()
2799 val |= config->early_output_mask; in clk_stromer_pll_configure()
2800 val |= config->pre_div_val; in clk_stromer_pll_configure()
2801 val |= config->post_div_val; in clk_stromer_pll_configure()
2802 val |= config->vco_val; in clk_stromer_pll_configure()
2803 val |= config->alpha_en_mask; in clk_stromer_pll_configure()
2804 val |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2806 mask = config->main_output_mask; in clk_stromer_pll_configure()
2807 mask |= config->aux_output_mask; in clk_stromer_pll_configure()
2808 mask |= config->aux2_output_mask; in clk_stromer_pll_configure()
2809 mask |= config->early_output_mask; in clk_stromer_pll_configure()
2810 mask |= config->pre_div_mask; in clk_stromer_pll_configure()
2811 mask |= config->post_div_mask; in clk_stromer_pll_configure()
2812 mask |= config->vco_mask; in clk_stromer_pll_configure()
2813 mask |= config->alpha_en_mask; in clk_stromer_pll_configure()
2814 mask |= config->alpha_mode_mask; in clk_stromer_pll_configure()
2816 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); in clk_stromer_pll_configure()
2818 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ in clk_stromer_pll_configure()
2819 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; in clk_stromer_pll_configure()
2820 val_u |= config->lock_det; in clk_stromer_pll_configure()
2822 mask_u = config->status_mask; in clk_stromer_pll_configure()
2823 mask_u |= config->lock_det; in clk_stromer_pll_configure()
2825 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); in clk_stromer_pll_configure()
2826 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_stromer_pll_configure()
2827 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_stromer_pll_configure()
2829 if (pll->flags & SUPPORTS_FSM_MODE) in clk_stromer_pll_configure()
2830 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); in clk_stromer_pll_configure()
2840 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, in clk_alpha_pll_stromer_determine_rate()
2849 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_set_rate() local
2856 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_set_rate()
2858 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_set_rate()
2859 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_set_rate()
2860 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_set_rate()
2863 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_set_rate()
2870 * Stromer PLL supports Dynamic programming. in clk_alpha_pll_stromer_set_rate()
2871 * It allows the PLL frequency to be changed on-the-fly without first in clk_alpha_pll_stromer_set_rate()
2874 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in clk_alpha_pll_stromer_set_rate()
2877 ret = wait_for_pll_update(pll); in clk_alpha_pll_stromer_set_rate()
2881 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_set_rate()
2898 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_stromer_plus_set_rate() local
2899 u32 l, alpha_width = pll_alpha_width(pll); in clk_alpha_pll_stromer_plus_set_rate()
2905 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); in clk_alpha_pll_stromer_plus_set_rate()
2909 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); in clk_alpha_pll_stromer_plus_set_rate()
2914 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in clk_alpha_pll_stromer_plus_set_rate()
2917 a <<= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_stromer_plus_set_rate()
2919 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in clk_alpha_pll_stromer_plus_set_rate()
2920 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_stromer_plus_set_rate()
2923 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_stromer_plus_set_rate()
2926 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); in clk_alpha_pll_stromer_plus_set_rate()
2930 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, in clk_alpha_pll_stromer_plus_set_rate()
2936 ret = wait_for_pll_enable_lock(pll); in clk_alpha_pll_stromer_plus_set_rate()
2938 pr_err("Wait for PLL enable lock failed [%s] %d\n", in clk_alpha_pll_stromer_plus_set_rate()
2944 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, in clk_alpha_pll_stromer_plus_set_rate()
2960 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, in clk_regera_pll_configure() argument
2963 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); in clk_regera_pll_configure()
2964 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_regera_pll_configure()
2965 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_regera_pll_configure()
2966 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); in clk_regera_pll_configure()
2967 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); in clk_regera_pll_configure()
2968 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_regera_pll_configure()
2969 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); in clk_regera_pll_configure()
2970 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); in clk_regera_pll_configure()
2971 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); in clk_regera_pll_configure()
2972 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); in clk_regera_pll_configure()
2973 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); in clk_regera_pll_configure()
2975 /* Set operation mode to STANDBY */ in clk_regera_pll_configure()
2976 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); in clk_regera_pll_configure()
2990 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) in qcom_clk_alpha_pll_configure() argument
2992 const struct clk_init_data *init = pll->clkr.hw.init; in qcom_clk_alpha_pll_configure()
2994 switch (GET_PLL_TYPE(pll)) { in qcom_clk_alpha_pll_configure()
2996 clk_lucid_ole_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
2999 clk_lucid_evo_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3002 clk_taycan_elu_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3005 clk_rivian_evo_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3008 clk_trion_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3011 clk_huayra_2290_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3014 clk_fabia_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3017 clk_agera_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3020 clk_pongo_elu_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3024 clk_zonda_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3028 clk_stromer_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3036 clk_alpha_pll_configure(pll, regmap, pll->config); in qcom_clk_alpha_pll_configure()
3039 WARN(1, "%s: invalid pll type\n", init->name); in qcom_clk_alpha_pll_configure()
3045 static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) in clk_alpha_pll_slew_update() argument
3050 regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE); in clk_alpha_pll_slew_update()
3051 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_slew_update()
3053 ret = wait_for_pll_update(pll); in clk_alpha_pll_slew_update()
3062 return wait_for_pll_enable_lock(pll); in clk_alpha_pll_slew_update()
3068 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_slew_set_rate() local
3077 return -EINVAL; in clk_alpha_pll_slew_set_rate()
3080 curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in clk_alpha_pll_slew_set_rate()
3082 pr_err("alpha pll: not in a valid vco range\n"); in clk_alpha_pll_slew_set_rate()
3083 return -EINVAL; in clk_alpha_pll_slew_set_rate()
3086 vco = alpha_pll_find_vco(pll, freq_hz); in clk_alpha_pll_slew_set_rate()
3088 pr_err("alpha pll: not in a valid vco range\n"); in clk_alpha_pll_slew_set_rate()
3089 return -EINVAL; in clk_alpha_pll_slew_set_rate()
3093 * Dynamic pll update will not support switching frequencies across in clk_alpha_pll_slew_set_rate()
3096 if (curr_vco->val != vco->val) in clk_alpha_pll_slew_set_rate()
3099 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false); in clk_alpha_pll_slew_set_rate()
3101 /* Ensure that the write above goes before slewing the PLL */ in clk_alpha_pll_slew_set_rate()
3105 return clk_alpha_pll_slew_update(pll); in clk_alpha_pll_slew_set_rate()
3112 * desired VCO range. So after bringing up the pll at calibration freq, set it
3117 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); in clk_alpha_pll_calibrate() local
3127 pr_err("alpha pll: no valid parent found\n"); in clk_alpha_pll_calibrate()
3128 return -EINVAL; in clk_alpha_pll_calibrate()
3131 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in clk_alpha_pll_calibrate()
3133 pr_err("alpha pll: not in a valid vco range\n"); in clk_alpha_pll_calibrate()
3134 return -EINVAL; in clk_alpha_pll_calibrate()
3142 calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2; in clk_alpha_pll_calibrate()
3148 return -EINVAL; in clk_alpha_pll_calibrate()
3151 clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false); in clk_alpha_pll_calibrate()
3153 /* Bringup the pll at calibration frequency */ in clk_alpha_pll_calibrate()
3156 pr_err("alpha pll calibration failed\n"); in clk_alpha_pll_calibrate()
3161 * PLL is already running at calibration frequency. in clk_alpha_pll_calibrate()
3162 * So slew pll to the previously set frequency. in clk_alpha_pll_calibrate()
3167 pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", in clk_alpha_pll_calibrate()
3170 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true); in clk_alpha_pll_calibrate()
3172 return clk_alpha_pll_slew_update(pll); in clk_alpha_pll_calibrate()