Lines Matching +full:0 +full:x9038
37 { 249600000, 2000000000, 0 },
42 .l = 0x1f,
43 .alpha = 0x4000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002067,
46 .test_ctl_val = 0x40000000,
47 .test_ctl_hi_val = 0x00000002,
48 .user_ctl_val = 0x00000101,
49 .user_ctl_hi_val = 0x00004805,
53 .offset = 0x0,
70 { 0x1, 2 },
75 .offset = 0x0,
94 .l = 0x2a,
95 .alpha = 0x1555,
96 .config_ctl_val = 0x20485699,
97 .config_ctl_hi_val = 0x00002067,
98 .test_ctl_val = 0x40000000,
99 .test_ctl_hi_val = 0x00000000,
100 .user_ctl_val = 0x00000101,
101 .user_ctl_hi_val = 0x00004805,
105 .offset = 0x1000,
122 { 0x1, 2 },
127 .offset = 0x1000,
146 .l = 0x64,
147 .alpha = 0x0,
148 .post_div_val = 0x3 << 8,
149 .post_div_mask = 0x3 << 8,
151 .main_output_mask = BIT(0),
153 .config_ctl_val = 0x20000800,
154 .config_ctl_hi_val = 0x400003d2,
155 .test_ctl_val = 0x04000400,
156 .test_ctl_hi_val = 0x00004000,
160 .offset = 0x2000,
188 { 0x1, 2 },
193 .offset = 0x2000,
212 .l = 0x14,
213 .alpha = 0x0,
214 .config_ctl_val = 0x20485699,
215 .config_ctl_hi_val = 0x00002067,
216 .test_ctl_val = 0x40000000,
217 .test_ctl_hi_val = 0x00000002,
218 .user_ctl_val = 0x00000001,
219 .user_ctl_hi_val = 0x00014805,
223 .offset = 0x3000,
240 { P_BI_TCXO, 0 },
250 { P_BI_TCXO, 0 },
264 { P_BI_TCXO, 0 },
276 { P_BI_TCXO, 0 },
286 { P_BI_TCXO, 0 },
298 { P_BI_TCXO, 0 },
312 { P_BI_TCXO, 0 },
324 { P_BI_TCXO, 0 },
338 { P_BI_TCXO, 0 },
350 { P_BI_TCXO, 0 },
360 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
361 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
362 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
363 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
364 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
369 .cmd_rcgr = 0x6010,
370 .mnd_width = 0,
383 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
384 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
385 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
390 .cmd_rcgr = 0xf004,
404 .cmd_rcgr = 0x10004,
418 F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
419 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
420 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
421 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
426 .cmd_rcgr = 0x9064,
427 .mnd_width = 0,
440 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0),
445 .cmd_rcgr = 0x5004,
446 .mnd_width = 0,
459 .cmd_rcgr = 0x5028,
460 .mnd_width = 0,
473 .cmd_rcgr = 0x504c,
474 .mnd_width = 0,
487 .cmd_rcgr = 0x5070,
488 .mnd_width = 0,
501 F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0),
502 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
503 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
504 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
509 .cmd_rcgr = 0x603c,
510 .mnd_width = 0,
523 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
524 F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
525 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
526 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
531 .cmd_rcgr = 0xe014,
532 .mnd_width = 0,
545 F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
546 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
547 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
548 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
549 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
554 .cmd_rcgr = 0x9010,
555 .mnd_width = 0,
569 .cmd_rcgr = 0x903c,
570 .mnd_width = 0,
583 .cmd_rcgr = 0xa010,
584 .mnd_width = 0,
598 .cmd_rcgr = 0xa034,
599 .mnd_width = 0,
612 .cmd_rcgr = 0xb00c,
613 .mnd_width = 0,
626 .cmd_rcgr = 0xb030,
627 .mnd_width = 0,
640 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
641 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
642 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
643 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
648 .cmd_rcgr = 0xc004,
649 .mnd_width = 0,
662 .cmd_rcgr = 0xc024,
663 .mnd_width = 0,
676 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
677 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
678 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
679 F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0),
680 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
685 .cmd_rcgr = 0x7010,
686 .mnd_width = 0,
700 F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0),
701 F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0),
702 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
703 F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
704 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
705 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
710 .cmd_rcgr = 0xd004,
711 .mnd_width = 0,
724 F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
725 F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0),
726 F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0),
727 F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
732 .cmd_rcgr = 0x11004,
733 .mnd_width = 0,
748 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
753 .cmd_rcgr = 0x4004,
767 .cmd_rcgr = 0x4024,
781 .cmd_rcgr = 0x4044,
795 .cmd_rcgr = 0x4064,
809 .cmd_rcgr = 0x4084,
823 F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0),
828 .cmd_rcgr = 0x6058,
829 .mnd_width = 0,
842 .halt_reg = 0x6070,
845 .enable_reg = 0x6070,
846 .enable_mask = BIT(0),
860 .halt_reg = 0x6054,
863 .enable_reg = 0x6054,
864 .enable_mask = BIT(0),
878 .halt_reg = 0x6038,
881 .enable_reg = 0x6038,
882 .enable_mask = BIT(0),
891 .halt_reg = 0x6028,
894 .enable_reg = 0x6028,
895 .enable_mask = BIT(0),
909 .halt_reg = 0x13004,
912 .enable_reg = 0x13004,
913 .enable_mask = BIT(0),
922 .halt_reg = 0xf01c,
925 .enable_reg = 0xf01c,
926 .enable_mask = BIT(0),
940 .halt_reg = 0x1001c,
943 .enable_reg = 0x1001c,
944 .enable_mask = BIT(0),
958 .halt_reg = 0x14010,
961 .enable_reg = 0x14010,
962 .enable_mask = BIT(0),
976 .halt_reg = 0x12004,
979 .enable_reg = 0x12004,
980 .enable_mask = BIT(0),
994 .halt_reg = 0x501c,
997 .enable_reg = 0x501c,
998 .enable_mask = BIT(0),
1012 .halt_reg = 0x5040,
1015 .enable_reg = 0x5040,
1016 .enable_mask = BIT(0),
1030 .halt_reg = 0x5064,
1033 .enable_reg = 0x5064,
1034 .enable_mask = BIT(0),
1048 .halt_reg = 0x5088,
1051 .enable_reg = 0x5088,
1052 .enable_mask = BIT(0),
1066 .halt_reg = 0x5020,
1069 .enable_reg = 0x5020,
1070 .enable_mask = BIT(0),
1084 .halt_reg = 0x5044,
1087 .enable_reg = 0x5044,
1088 .enable_mask = BIT(0),
1102 .halt_reg = 0x5068,
1105 .enable_reg = 0x5068,
1106 .enable_mask = BIT(0),
1120 .halt_reg = 0x508c,
1123 .enable_reg = 0x508c,
1124 .enable_mask = BIT(0),
1138 .halt_reg = 0xe02c,
1141 .enable_reg = 0xe02c,
1142 .enable_mask = BIT(0),
1156 .halt_reg = 0xe00c,
1159 .enable_reg = 0xe00c,
1160 .enable_mask = BIT(0),
1169 .halt_reg = 0x9080,
1172 .enable_reg = 0x9080,
1173 .enable_mask = BIT(0),
1182 .halt_reg = 0x9028,
1185 .enable_reg = 0x9028,
1186 .enable_mask = BIT(0),
1200 .halt_reg = 0x907c,
1203 .enable_reg = 0x907c,
1204 .enable_mask = BIT(0),
1218 .halt_reg = 0x9054,
1221 .enable_reg = 0x9054,
1222 .enable_mask = BIT(0),
1236 .halt_reg = 0x9038,
1239 .enable_reg = 0x9038,
1240 .enable_mask = BIT(0),
1254 .halt_reg = 0xa058,
1257 .enable_reg = 0xa058,
1258 .enable_mask = BIT(0),
1267 .halt_reg = 0xa028,
1270 .enable_reg = 0xa028,
1271 .enable_mask = BIT(0),
1285 .halt_reg = 0xa054,
1288 .enable_reg = 0xa054,
1289 .enable_mask = BIT(0),
1303 .halt_reg = 0xa04c,
1306 .enable_reg = 0xa04c,
1307 .enable_mask = BIT(0),
1321 .halt_reg = 0xa030,
1324 .enable_reg = 0xa030,
1325 .enable_mask = BIT(0),
1339 .halt_reg = 0xb054,
1342 .enable_reg = 0xb054,
1343 .enable_mask = BIT(0),
1352 .halt_reg = 0xb024,
1355 .enable_reg = 0xb024,
1356 .enable_mask = BIT(0),
1370 .halt_reg = 0xb050,
1373 .enable_reg = 0xb050,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0xb048,
1391 .enable_reg = 0xb048,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0xb02c,
1409 .enable_reg = 0xb02c,
1410 .enable_mask = BIT(0),
1424 .halt_reg = 0xc01c,
1427 .enable_reg = 0xc01c,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0xc044,
1445 .enable_reg = 0xc044,
1446 .enable_mask = BIT(0),
1460 .halt_reg = 0xc03c,
1463 .enable_reg = 0xc03c,
1464 .enable_mask = BIT(0),
1478 .halt_reg = 0x7040,
1481 .enable_reg = 0x7040,
1482 .enable_mask = BIT(0),
1496 .halt_reg = 0x703c,
1499 .enable_reg = 0x703c,
1500 .enable_mask = BIT(0),
1514 .halt_reg = 0x7038,
1517 .enable_reg = 0x7038,
1518 .enable_mask = BIT(0),
1527 .halt_reg = 0x7028,
1530 .enable_reg = 0x7028,
1531 .enable_mask = BIT(0),
1545 .halt_reg = 0xd01c,
1548 .enable_reg = 0xd01c,
1549 .enable_mask = BIT(0),
1563 .halt_reg = 0x1101c,
1566 .enable_reg = 0x1101c,
1567 .enable_mask = BIT(0),
1581 .halt_reg = 0x401c,
1584 .enable_reg = 0x401c,
1585 .enable_mask = BIT(0),
1599 .halt_reg = 0x403c,
1602 .enable_reg = 0x403c,
1603 .enable_mask = BIT(0),
1617 .halt_reg = 0x405c,
1620 .enable_reg = 0x405c,
1621 .enable_mask = BIT(0),
1635 .halt_reg = 0x407c,
1638 .enable_reg = 0x407c,
1639 .enable_mask = BIT(0),
1653 .halt_reg = 0x409c,
1656 .enable_reg = 0x409c,
1657 .enable_mask = BIT(0),
1671 .halt_reg = 0x1400c,
1674 .enable_reg = 0x1400c,
1675 .enable_mask = BIT(0),
1684 .halt_reg = 0xe034,
1687 .enable_reg = 0xe034,
1688 .enable_mask = BIT(0),
1697 .gdscr = 0x6004,
1698 .en_rest_wait_val = 0x2,
1699 .en_few_wait_val = 0x2,
1700 .clk_dis_wait_val = 0xf,
1709 .gdscr = 0x7004,
1710 .en_rest_wait_val = 0x2,
1711 .en_few_wait_val = 0x2,
1712 .clk_dis_wait_val = 0xf,
1721 .gdscr = 0x9004,
1722 .en_rest_wait_val = 0x2,
1723 .en_few_wait_val = 0x2,
1724 .clk_dis_wait_val = 0xf,
1732 .gdscr = 0xa004,
1733 .en_rest_wait_val = 0x2,
1734 .en_few_wait_val = 0x2,
1735 .clk_dis_wait_val = 0xf,
1743 .gdscr = 0xb004,
1744 .en_rest_wait_val = 0x2,
1745 .en_few_wait_val = 0x2,
1746 .clk_dis_wait_val = 0xf,
1754 .gdscr = 0x14004,
1755 .en_rest_wait_val = 0x2,
1756 .en_few_wait_val = 0x2,
1757 .clk_dis_wait_val = 0xf,
1868 .max_register = 0x16000,